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10 nm process

The 10 nm process is a semiconductor manufacturing technology node characterized by transistor gate lengths and other critical features measuring approximately 10 nanometers, representing a significant advancement in integrated circuit fabrication that enables higher transistor densities, enhanced performance, and reduced power consumption compared to prior 14 nm and 16 nm nodes.^[1] This node primarily employs FinFET (Fin Field-Effect Transistor) architectures to mitigate short-channel effects and improve electrostatic control, alongside multi-patterning lithography techniques—such as quadruple or triple patterning—to achieve the required precision, as extreme ultraviolet (EUV) lithography was not yet mature for widespread adoption at this scale.^[2] Key benefits include up to 2.7 times greater transistor density over 14 nm processes, 20-30% performance gains, and 30-40% power reductions, facilitating more efficient mobile, computing, and AI applications.^[2] Major foundries pursued distinct implementations of the 10 nm process, with Samsung Electronics leading in commercialization by initiating mass production of 10 nm FinFET system-on-chips (SoCs) on October 17, 2016, offering 27% higher performance or 40% lower power than its 14 nm predecessor through advanced 3D transistor structures and triple-patterning for greater design flexibility.^[3] TSMC began risk production in late 2015 and entered volume manufacturing in early 2017 for clients like Apple and MediaTek, emphasizing competitive area efficiency and integration of novel dielectric schemes to minimize capacitance.^[4] Intel, originally targeting high-volume manufacturing in 2016, encountered yield challenges from complex multi-patterning (up to six exposures), delaying revenue shipments until early 2018 for its Cannon Lake processors and achieving full volume in 2019, with enhanced versions like Intel 7 (10 nm SuperFin) still experiencing demand exceeding supply as of November 2025 amid capacity conversions to newer nodes, ultimately delivering 100 million transistors per square millimeter and features like cobalt interconnects for improved reliability.^[2]^[5] GlobalFoundries opted to skip dedicated 10 nm development, jumping directly to 7 nm research in 2016 to focus resources on mature nodes amid competitive pressures; however, it suspended 7 nm development in 2018.^[6]^[7] The 10 nm node marked a transitional era in Moore's Law scaling, bridging planar transistors to more advanced 3D structures, though variations in density and performance across foundries—such as Intel's 100.8 million transistors/mm² versus Samsung's initial 52 million—highlighted non-standardized naming conventions where "10 nm" often reflected marketing rather than literal dimensions.^[8] Its adoption accelerated SoC designs for smartphones and servers, but delays and costs spurred rapid evolution toward 7 nm and below, with EUV integration in later iterations.^[2]

Introduction

Definition and nomenclature

The 10 nm process refers to a generation of semiconductor manufacturing technology used to fabricate integrated circuits, particularly metal-oxide-semiconductor field-effect transistors (MOSFETs), where key interconnect and transistor features are scaled to dimensions around 10 nanometers. This node follows the 14 nm process in the progression outlined by the International Technology Roadmap for Semiconductors (ITRS), emphasizing improvements in transistor density, power efficiency, and performance through advancements like FinFET architectures.^[9] In practice, the "10 nm" label functions as an industry marketing term rather than a literal measurement of any specific physical dimension, such as gate length. While ITRS guidelines predicted a physical gate length of around 7 nm for high-performance logic, actual implementations, such as Intel's, featured gate lengths of approximately 18 nm—larger than the node designation—highlighting the decoupling from exact geometry. Originating from ITRS guidelines, the nomenclature ties the node to metrics like the metal-1 (M1) half-pitch for logic processes, approximately 10 nm, but it broadly signifies equivalent scaling that includes non-dimensional enhancements beyond pure size reduction. This decoupling from exact geometry allows manufacturers to highlight overall process improvements without strict adherence to a single feature size.^[9]^[10] The term's application differs between logic and memory technologies. For logic nodes used in CPUs and GPUs, "10 nm" emphasizes transistor performance and integration density, often measured in millions of transistors per square millimeter. In contrast, for memory like DRAM, the "10 nm class" (e.g., designations such as 1x, 1y, or 1z) specifically references the half-pitch of memory cell arrays, while NAND flash employs it for 3D-stacked layer counts rather than planar scaling. This distinction arises because memory prioritizes storage density and cost per bit, whereas logic focuses on speed and logic function complexity.^[11] Node naming conventions evolved historically from direct correlations with physical features, such as gate length in nodes up to about 22 nm, to more abstract indicators of density and performance metrics thereafter. This shift, accelerated post-22 nm due to scaling limitations like quantum effects and manufacturing variability, enabled continued progress under Moore's law without implying proportional dimensional reduction. For example, Intel's implementation of the 10 nm process achieves a logic transistor density of approximately 100 million transistors per square millimeter, illustrating the focus on areal efficiency over precise linear scales.^[12]^[1]

Significance in Moore's law scaling

The 10 nm process represented a pivotal advancement in sustaining Moore's law, which posits that the number of transistors on a chip roughly doubles every two years, driving exponential improvements in computing power. By achieving approximately a 2.7-fold increase in transistor density over the preceding 14 nm node—reaching up to 100.8 million transistors per square millimeter—this node enabled the fabrication of smaller dies with significantly higher core counts, thereby extending the trajectory of performance scaling without proportionally increasing chip area. This density leap was essential for maintaining the economic and technological momentum of semiconductor evolution, as it aligned with the predicted doubling of integration levels.^[13]^[14] Performance enhancements at the 10 nm node further underscored its role in Moore's law progression, delivering roughly 25% higher speed at iso-power or a 45% reduction in power consumption for equivalent performance compared to 14 nm processes. These gains stemmed from improved transistor efficiency and reduced parasitic capacitances, allowing chips to operate faster or more efficiently in power-constrained environments. Industry analyses highlight that such improvements typically translated to 20-30% performance boosts or 35-45% power savings across benchmarks, bolstering applications requiring high computational throughput.^[15] Economically, the 10 nm process lowered the cost per transistor despite elevated fabrication expenses for advanced tools and materials, making it viable for widespread deployment in mobile SoCs, server CPUs, and AI accelerators. This cost efficiency accelerated adoption by enabling more transistors per dollar, which in turn fueled innovations in energy-efficient computing and data-intensive workloads. At the same time, the node served as a critical transition where classical 2D planar scaling encountered fundamental physical limits, prompting reliance on 3D transistor architectures like FinFET to preserve density and efficiency gains.^[8]^[16]

Technological Aspects

Transistor architecture and materials

The 10 nm process universally adopted FinFET (tri-gate) transistors as the standard architecture for high-performance logic, replacing planar MOSFETs to better control short-channel effects and enable continued scaling. These tri-gate structures feature three-dimensional silicon fins that wrap around the gate, improving gate control and reducing leakage compared to planar designs. Typical dimensions include a fin pitch of approximately 30-42 nm and a gate length of around 18-20 nm, allowing for tighter packing while maintaining electrostatic integrity.^[17]^[18]^[2] Material advancements were critical to achieving performance targets at this node. High-k metal gate (HKMG) stacks, in their fifth generation of refinement, replaced traditional SiO<sub>2</sub> dielectrics with materials like HfO<sub>2</sub> to reduce gate leakage while supporting equivalent oxide thickness scaling below 1 nm. Strained silicon channels, enhanced through seventh-generation techniques such as embedded SiGe for pMOS and tensile strain for nMOS, boosted carrier mobility by up to 30% over unstrained silicon, mitigating velocity saturation issues. Cobalt emerged as a key contact material, forming low-resistance interfaces with silicon and reducing source/drain contact resistivity by approximately 60% compared to nickel-platinum silicides used in prior nodes.^[17]^[19] To minimize parasitic effects, the 10 nm process introduced self-aligned contacts (SAC), where contact metals are etched and filled after gate formation, enabling overlap with the gate without lithography misalignment and reducing contact resistance. Air-gapped interconnects were selectively implemented in local metal layers to lower parasitic capacitance by up to 17%, achieved by decomposing the dielectric after copper patterning to create voids that act as low-k (k≈1) regions without compromising mechanical stability. These innovations collectively addressed RC delay challenges as feature sizes shrank.^[17]^[20] Transistor density at the 10 nm node scaled approximately as \rho \propto \frac{1}{L_g \cdot W_{eff}}, where L_g is the gate length (∼10-20 nm) and W_{eff} is the effective channel width determined by fin height and number. This relation, adapted from classical MOSFET scaling, explains the roughly 2× density improvement over prior planar generations by reducing L_g and optimizing W_{eff} through multi-fin configurations, though FinFETs partially decouple width scaling from density via vertical fin stacking.^[21]^[22]

Lithography and fabrication techniques

The 10 nm semiconductor process predominantly utilized 193 nm immersion lithography enhanced by multiple patterning techniques to overcome the resolution limits of deep ultraviolet (DUV) light in the pre-extreme ultraviolet (EUV) era, enabling the patterning of features with effective half-pitches as small as 40 nm.^[23] This approach involved sequential litho-etch steps, where a single exposure was decomposed into multiple masks to double or quadruple the pattern density, particularly for critical layers like fins and metal lines. For instance, quadruple patterning was applied to achieve the tight spacing required for local interconnects, mitigating the diffraction constraints of 193 nm wavelengths by introducing self-aligned spacers and trim etches.^[24] To address the complexities of multiple patterning, directed self-assembly (DSA) of block copolymers was introduced as a complementary technique in pilot implementations, offering a bottom-up method to refine patterns beyond traditional optical limits for sub-10 nm features.^[25] DSA leverages the natural phase separation of polymer materials guided by pre-patterned templates to form precise nanostructures, such as line-space arrays for contact holes or vias, reducing the need for additional masks in select 10 nm variants.^[26] In parallel, early EUV pilots emerged for metal layers in later iterations of the 10 nm process, utilizing 13.5 nm wavelength sources to simplify patterning by enabling single-exposure resolution comparable to quadruple DUV, though limited by source power and availability during initial adoption.^[27] Fabrication sequences in the 10 nm node incorporated atomic layer deposition (ALD) for conformal gate stack formation, depositing high-k dielectrics and work-function metals layer-by-layer to ensure uniformity over three-dimensional FinFET structures with thicknesses below 5 nm.^[28] Selective etching processes followed, employing plasma-based techniques to anisotropically trim silicon fins to widths around 7-10 nm while preserving adjacent materials, thus defining the channel dimensions critical for gate-all-around control.^[29] Chemical mechanical polishing (CMP) was integral for post-deposition planarization, using abrasive slurries to achieve sub-nanometer surface roughness across inter-layer dielectrics and metals, preventing topography-induced defects in subsequent patterning steps.^[30] These techniques confronted significant challenges, including maintaining overlay accuracy below 2 nm (3σ) across multiple exposures to align patterns without shorting or misalignment in dense arrays, and achieving defect densities under 0.1 defects per cm² to ensure viable yields.^[31] Advanced metrology and process controls, such as scatterometry for edge placement error monitoring, were essential to mitigate stochastic variations and pitch-walking errors inherent in multiple patterning.^[32]

Logic Process Nodes

Intel's 10 nm implementation

Intel's 10 nm process represents a significant advancement in semiconductor manufacturing, achieving a logic transistor density of 100.8 million transistors per square millimeter (MTr/mm²), which is 2.7 times higher than its preceding 14 nm node.^[33] This density metric, based on Intel's standard cell measurements, positions the process as highly compact for logic applications, enabling more efficient integration of components in integrated circuits. The architecture relies on third-generation FinFET transistors, featuring a 54 nm gate pitch and 36 nm minimum metal pitch, which support up to 25% better performance and 45% lower power consumption compared to 14 nm equivalents.^[33] Additionally, Intel incorporated cobalt for local interconnects in the finest metal layers (M0 and M1) to address electromigration challenges and reduce via resistance by up to 2x, marking the first high-volume use of cobalt in such layers despite its higher resistivity than copper.^[34] The initial implementation of Intel's 10 nm process debuted in 2018 with the Cannon Lake family of mobile processors, serving as a limited-production entry point to validate the node in real-world devices.^[35] Subsequent refinements followed, including the 10 nm+ variant in 2019 for the Ice Lake processors, which introduced minor optimizations for mobile and server applications, and the 10 nm SuperFin enhancement in 2020. SuperFin, Intel's key upgrade to the 10 nm lineup, featured taller fins, improved contact structures, and a thinner barrier for interconnects that reduced resistance by 30%, delivering an intranode performance uplift of approximately 18-20% over prior 10 nm versions while maintaining the same density.^[36] This variant powered the Tiger Lake mobile processors, emphasizing higher clock speeds and efficiency for client computing.^[37] Although Intel planned a transition to RibbonFET gate-all-around transistors as a successor to FinFET for future nodes, the 10 nm process remained firmly based on FinFET architecture across all variants, with RibbonFET implementations deferred to later technologies like Intel 20A.^[38] In terms of competitiveness, Intel's 10 nm density is roughly equivalent to TSMC's N7 (7 nm) process, which achieves around 96-100 MTr/mm², but Intel's design emphasizes higher drive currents in high-performance cells to support superior single-threaded performance metrics.^[39]^[40]

TSMC and Samsung 10 nm processes

TSMC's 10 nm process, designated as N10, achieved a transistor density of approximately 55 million transistors per square millimeter (MTr/mm²).^[41] The company entered risk production in the first quarter of 2016 and began high-volume manufacturing in early 2017, enabling rapid adoption in mobile applications.^[42] This node supported variants tailored for high-performance computing and low-power requirements, with the N10P low-power option optimizing energy efficiency for battery-constrained devices.^[43] Samsung developed its 10 nm family with the initial 10LPE (Low Power Early) variant entering mass production in October 2016, followed by the enhanced 10LPP (Low Power Plus) in April 2017.^[44] The 10LPP process delivered a transistor density of around 58 MTr/mm².^[41] While primarily relying on multiple patterning lithography, Samsung incorporated early optimizations that paved the way for extreme ultraviolet (EUV) lithography in subsequent nodes, including reduced complexity for contact layers.^[4] A key distinction between the two foundries lies in their customer ecosystems and application focus. TSMC's N10 was prominently used in mobile system-on-chips (SoCs), such as Apple's A11 Bionic processor for the iPhone X, emphasizing seamless integration for high-volume consumer devices.^[45] In contrast, Samsung's 10 nm processes powered its own Exynos 8895 SoC for the Galaxy S8 series and Qualcomm's Snapdragon 835, which featured in select regional variants of the same devices, highlighting Samsung's dual role as both foundry and chip designer.^[46] Both TSMC and Samsung's 10 nm nodes provided roughly a 30% reduction in die area compared to their preceding 16/14 nm generations, alongside improvements in performance and power efficiency that advanced mobile computing capabilities.^[4] This scaling enabled denser integration of components like CPUs, GPUs, and modems without proportional increases in power draw.

GlobalFoundries and other efforts

GlobalFoundries initially pursued a 10 nm process as part of its technology roadmap following the 2014 acquisition of IBM's microelectronics business, which included commitments to develop 10 nm semiconductors for IBM's server processors. However, in 2016, the company announced it would skip the 10 nm node entirely, opting instead to jump directly to 7 nm development to accelerate progress and avoid what it described as a marginal "half-node" improvement.^[47] This decision was driven by the escalating capital intensity of advanced node development, with estimates indicating costs exceeding $10 billion to bring a new process like 10 nm to high-volume manufacturing, compounded by challenges in achieving viable yields without extreme ultraviolet (EUV) lithography, which relies on costly multi-patterning techniques at that scale.^[48]^[7] By 2018, GlobalFoundries further halted its 7 nm program indefinitely, citing unsustainable financial demands and lengthy development timelines that threatened the company's viability without guaranteed returns. The pivot shifted focus to optimized 12 nm and 7 nm-class processes tailored for analog, radio-frequency (RF), and specialty applications, such as embedded memory and power management, rather than competing in high-volume logic markets dominated by rivals. This strategic refocus allowed GlobalFoundries to leverage existing fabs for differentiated offerings, including 22FDX silicon-on-insulator technology, emphasizing performance-per-watt efficiency in niche sectors like automotive and IoT.^[49]^[50] Other efforts in the 10 nm space were similarly limited. IBM contributed partially through early alliances, such as its 2013 collaboration with United Microelectronics Corporation (UMC) on 10 nm CMOS development, but produced no standalone 10 nm process after divesting its semiconductor operations to GlobalFoundries. Semiconductor Manufacturing International Corporation (SMIC), a key Chinese foundry, lagged significantly behind global leaders in advanced nodes, beginning mass production of 14 nm FinFET chips around 2020 and achieving 7 nm production in late 2022 using deep ultraviolet (DUV) lithography, though limited by low yields and volumes due to U.S. export restrictions on extreme ultraviolet (EUV) tools and other advanced equipment.^[51]^[52] The legacy of GlobalFoundries' 10 nm research endures in its subsequent low-power process optimizations, where insights into FinFET scaling and materials informed enhancements to 12 nm platforms for RF and mixed-signal applications, enabling better integration in 5G and edge computing devices without pursuing bleeding-edge density.^[7]

Production History

Key milestones and timelines

Intel announced its 10 nm process node in 2014 as part of its manufacturing roadmap, with an initial target for volume production in 2016. By 2016, TSMC commenced risk production of its N10 (10 nm) process, enabling early validation for customer designs. In the same year, Samsung achieved the first tape-out for 10 nm logic chips, advancing toward system-on-chip implementations.^[53]^[3] In 2017, Samsung began mass production of its second-generation 10 nm process variant, 10LPP, offering improved performance and power efficiency over the initial 10LPE. TSMC transitioned to volume shipments of N10 chips that year, supporting high-volume mobile applications. Meanwhile, Intel delayed its 10 nm production ramp to 2018 due to yield challenges.^[44] Intel shipped its first 10 nm-based processors, the Cannon Lake family, in low volumes in 2018, primarily for mobile segments. In the same year, GlobalFoundries halted advanced node development, having skipped dedicated 10 nm efforts in 2016 to focus on 7 nm before opting for enhancements to its 12/14 nm nodes instead of leading-edge scaling.^[54]^[7] From 2017 to 2020, 10 nm processes saw widespread adoption in mobile devices, exemplified by Apple's A11 Bionic chip in the iPhone X using TSMC's 10 nm and Samsung's Exynos 9810 in the Galaxy S9 series on its 10 nm LPP. By 2025, the 10 nm process had matured into a reliable node across manufacturers, with enhancements such as Intel's 10 nm SuperFin introduced in 2020 for products like Tiger Lake, and further optimizations under Intel 7 for later generations like Meteor Lake in 2023, delivering significant intra-node improvements in performance and density.

Challenges in yield and adoption

One of the primary technical hurdles in the 10 nm process was achieving acceptable yields, particularly for Intel's implementation, where initial production suffered from low yields due to the complexity of quadruple patterning techniques required to pattern features without extreme ultraviolet (EUV) lithography. This multi-patterning approach, involving multiple exposure steps, led to high defect densities from overlay errors and process variations, delaying high-volume manufacturing.^[2] By 2019, Intel reported significant improvements in yields as process optimizations and learning curves took effect, enabling broader deployment in products like Ice Lake processors.^[55] Economic barriers further complicated adoption, as the delay in EUV readiness forced reliance on deep ultraviolet (DUV) lithography with multi-patterning, which escalated mask set costs due to the need for multiple, precisely aligned masks. This increased fabrication expenses compared to prior nodes, straining budgets for integrated device manufacturers (IDMs) like Intel that bore full development risks.^[56] In contrast, pure-play foundries such as TSMC mitigated these costs through high-volume mobile contracts, amortizing investments over large-scale production runs.^[57] Adoption faced substantial delays, exemplified by Intel's over two-year slippage from its original 2016 target to 2019 volume ramp-up, allowing competitors like TSMC to introduce 7 nm nodes by 2018 and capture market share in high-performance computing. These setbacks created internal pressures for IDMs, as prolonged 14 nm reliance eroded competitive edges in power efficiency and density.^[35] From a 2025 perspective, the 10 nm process has become cost-effective for legacy and mid-range applications, with mature yields supporting ongoing use in embedded systems, though it is largely overshadowed by sub-5 nm nodes driving innovation in AI and mobile sectors.^[58]

DRAM 10 nm Class

Definition and generational progression

The 10 nm class in DRAM fabrication refers to a category of process nodes characterized by a half-pitch ranging from 10 to 19 nm, a metric that measures half the center-to-center distance of repeating memory cell features such as active areas.^[59] This classification is distinct from logic semiconductor nodes, as it prioritizes the scaling of capacitor height, bitline pitch, and wordline dimensions to maintain cell capacitance while shrinking overall footprint, enabling higher bit densities without immediate reliance on entirely new transistor architectures.^[60] The focus on these elements addresses the unique challenges of DRAM, where maintaining sufficient charge storage in shrinking cells drives innovations in materials and patterning, rather than gate length reductions seen in logic.^[61] The generational progression within the 10 nm class began with the 1x generation around 2016, featuring a half-pitch of approximately 17 nm (within 16-19 nm range), marking the initial entry into sub-20 nm scaling for commercial DRAM production.^[62] This was followed by the 1y generation in 2017 at about 15 nm half-pitch (14-16 nm), the 1z in 2019 at roughly 13 nm (12-14 nm), and the 1a/1α in 2021-2023 targeting around 12-14 nm.^[62] Subsequent advancements include the 1b/1β generation entering production in 2024 with half-pitches near 12 nm, and the 1c/1γ in 2025 aiming for 10-11 nm, representing the sixth iteration in this lineage.^[63] These steps reflect iterative refinements in extreme ultraviolet (EUV) lithography and multi-patterning to achieve tighter pitches while managing variability, with EUV adoption becoming prominent from 1a onward to reduce patterning complexity.^[64]^[65] Each generation typically delivers about a 1.3x increase in bit density over the prior one, driven by reduced cell sizes and optimized layouts, though exact gains vary by implementation.^[59] For instance, the 1z generation achieved densities around 0.25 Gb/mm² in DDR4 configurations, supporting 16 Gb dies with enhanced performance metrics like up to 3,200 Mbps transfer rates.^[66]^[67] Later generations, such as 1b and 1c, introduce precursors to 3D stacking, including taller capacitors and vertical channel explorations, to extend scaling beyond planar limits and prepare for future multi-layer architectures amid slowing two-dimensional shrinks.^[68]

Implementations by major manufacturers

Samsung pioneered the 10 nm class DRAM with its first-generation 1x process in 2016, enabling high-density memory solutions integrated into various applications. This was followed by the 1z process in 2019, which supported 8 Gb DDR4 chips with enhanced performance and power efficiency for premium memory uses. By 2025, Samsung advanced to the sixth-generation 1c process, achieving yields exceeding 70% and positioning it for HBM4 production, with mass production ramps supporting AI and high-bandwidth needs.^[69]^[70] SK Hynix introduced its 1y process in 2017 as part of the early 10 nm class progression, focusing on density improvements for mainstream DRAM. In 2025, the company achieved a milestone with the 1c process, the world's first sixth-generation 10 nm class technology tailored for DDR5 16 Gb chips, emphasizing AI-optimized performance and energy efficiency. This development allowed for up to 30% power savings in data center applications compared to prior generations.^[64]^[71] Micron's 1α process, the fourth generation in the 10 nm class and launched in 2021, enabled high-density DDR5 solutions with significant advancements in speed and low power for mobile and server uses, including support for 24 Gb dies. The company emphasized domestic U.S. manufacturing to bolster supply chain resilience. Looking ahead, Micron announced plans in 2025 to skip further 10 nm refinements and transition directly to a 9 nm process by 2026, accelerating beyond the current node.^[59]^[72] These implementations found applications in DDR4 and DDR5 for computing, LPDDR5 for mobile devices, and HBM3/HBM4 for GPU acceleration in AI workloads by 2025. In 2025, all three manufacturers—Samsung, SK Hynix, and Micron—reached maturity in their 1c or equivalent 1γ processes, achieving areal densities around 0.3-0.4 Gb/mm² to meet escalating demands for high-capacity memory.^[73]^[74]

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