Fact-checked by Grok 2 weeks ago

IMEC

The India–Middle East–Europe Economic Corridor (IMEC) is a proposed multinational infrastructure project to create an integrated network of rail, road, maritime, energy, and digital connectivity linking India with Europe through the Middle East.^[1]^[2] Announced via a memorandum of understanding signed on 9 September 2023 at the G20 Leaders' Summit in New Delhi, IMEC involves key participants including India, the United States, the United Arab Emirates, Saudi Arabia, Israel, Jordan, France, Germany, Italy, and the European Union.^[1]^[3] The corridor consists of an eastern segment connecting India to the Arabian Gulf via sea and rail, and a northern segment linking the Gulf to Europe through Jordan, Israel, and ports in Italy or Greece, with provisions for electricity transmission lines, hydrogen pipelines, and high-speed data cables.^[2]^[4] Intended to cut transit times by up to 40% compared to Suez Canal routes, reduce carbon emissions, and boost trade volumes potentially handling 1.5 million twenty-foot equivalent units annually, IMEC represents a strategic effort to diversify supply chains and counterbalance China's Belt and Road Initiative amid rising geopolitical uncertainties.^[5]^[6] However, implementation has faced significant delays due to regional conflicts, including the Israel-Hamas war and Houthi disruptions in the Red Sea, highlighting vulnerabilities in cross-border cooperation within volatile areas.^[5]^[7]

Overview

Mission and Organizational Scope

Imec functions as an independent, non-profit research and development hub dedicated to pioneering breakthroughs in nanoelectronics and digital technologies through collaborative, pre-competitive efforts. Established in 1984 as the Interuniversity Microelectronics Centre (IMEC), its foundational purpose was to integrate academic expertise with industrial capabilities, addressing gaps in semiconductor R&D by conducting investigations ahead of commercial timelines, typically 3 to 10 years into the future.^[8]^[9] This mission centers on generating empirical innovations that resolve causal constraints in device scaling and integration, such as quantum effects and thermal limits, while extending to practical domains like AI hardware, health diagnostics, and low-power computing without deference to non-technical priorities.^[8] The organizational scope prioritizes verifiable prototyping and pilot-scale validation over theoretical speculation, utilizing advanced infrastructure like 300mm wafer pilot lines to test mechanisms for sustainable chip advancements. This approach ensures outputs are grounded in measurable performance gains, facilitating transitions from lab concepts to manufacturable solutions via shared risk models that lower barriers for participants.^[8]^[10] Imec's independence enables neutral facilitation of multi-stakeholder consortia, where over 200 universities and industry leaders co-develop intellectual property under equitable licensing, distinct from proprietary pursuits that constrain early-stage knowledge exchange.^[10]^[11] By emphasizing causal realism—dissecting fundamental physical and process interactions—imec sustains a track record of enabling scalable technologies, such as enhancements in lithography resolution and vertical stacking paradigms, through data-backed iterations rather than unsubstantiated projections. This scope positions it as a bridge for ecosystem-wide progress, where empirical milestones inform broader digital transformation without competitive silos.^[10]^[9]

Key Metrics and Global Presence

Imec employs more than 5,500 researchers and staff from over 100 nationalities as of 2024.^[12]^[13] Its annual revenue reached €1.034 billion in 2024, with operating expenses totaling €993 million, funded predominantly through contracts with industry partners and public institutions rather than core government subsidies.^[14]^[15] The organization maintains its headquarters in Leuven, Belgium, alongside other Belgian sites including facilities in Hasselt and Genk for specialized R&D and incubation activities.^[16] Internationally, imec operates campuses and offices across Europe (including the Netherlands and UK), the United States (with centers in Florida for cryogenic and advanced packaging technologies, Boston for innovation ecosystems, California, and Purdue University in the Midwest), and Asia (Taiwan, China, India, and Japan).^[8]^[17]^[18] This footprint supports collaborative projects in nanoelectronics and digital technologies, excluding dedicated photonics expansions like the Malaga site established in 2017, which aligns with broader European R&D networks. Imec's global influence is evidenced by its partnerships with leading semiconductor firms such as ASML, Intel, and TSMC, alongside a network facilitating joint programs.^[11] It has produced more than 130 spin-offs since 1984 and supported over 300 startups via initiatives like imec.istart, while accumulating over 1,600 patent families, many co-owned with industry collaborators.^[19]^[8]^[20] These outputs underscore imec's role in translating research into commercial applications without direct equity stakes in most cases.^[21]

History

Founding and Early Development (1984–1990s)

IMEC was founded on January 5, 1984, in Leuven, Belgium, as an independent non-profit research center by the Flemish government, with Prof. Roger Van Overstraeten, a KU Leuven professor and Stanford PhD alumnus, serving as its inaugural president and CEO.^[22]^[9] The initiative stemmed from a 1982 Flemish program to elevate the region's microelectronics capabilities against U.S. and Japanese industry leaders, motivated by observations of Silicon Valley's rapid innovation and the need for Europe to foster domestic expertise in scaling integrated circuits.^[9]^[22] Initial funding, totaling around €62 million from the regional government and supporting universities including KU Leuven, enabled the immediate setup of a 200 mm cleanroom and hiring of about 70 staff, prioritizing CMOS process modules such as wet cleaning and silicide formation.^[23]^[22]^[24] From inception, IMEC's core focus was empirical advancement of CMOS technology for integrated circuit design, aiming to extend Moore's Law by shrinking transistor dimensions while maintaining performance and efficiency gains.^[22] Early R&D emphasized pre-competitive validation of scaling fundamentals, including partnerships with equipment vendors for access to state-of-the-art lithography and deposition tools, which allowed testing of sub-micron feature viability through iterative fabrication runs.^[22]^[24] This infrastructure-driven approach, rooted in first-hand replication of industry challenges rather than theoretical modeling alone, positioned IMEC to demonstrate feasible reductions in gate lengths and interconnect sizes by the late 1980s.^[22] The 1990s marked a pivot to structured industry consortia, with IMEC launching its first two Industry Affiliation Programs (IAPs) in 1992–1994 to pool resources for collaborative CMOS development amid escalating competition from Asian foundries.^[25] These programs facilitated joint empirical work on process integration, yielding advancements in logic and analog ICs compatible with emerging 0.25 μm nodes by decade's end, verified through shared pilot line outputs and IP licensing frameworks.^[25]^[26] Under subsequent leadership including CEO Gilbert Declerck, this model emphasized causal links between material innovations and yield improvements, countering scaling barriers like leakage without relying on unsubstantiated projections.^[22]

Expansion and Maturation (2000s–2010s)

During the 2000s, imec intensified its CMOS scaling efforts, demonstrating key breakthroughs toward the 45 nm node, including high-k metal gate stacks and multiple-gate transistors that enabled functional amplifiers and oscillators in sub-45 nm analog/RF-CMOS prototypes by 2008.^[27] These achievements relied on empirical optimizations to counter short-channel effects and leakage, sustaining transistor density gains amid diminishing returns from classical scaling.^[28] Concurrently, imec expanded beyond pure nanoelectronics by partnering with TNO to establish the Holst Centre in Eindhoven in 2005, focusing on wireless autonomous sensor networks for health monitoring, which yielded early prototypes of body-worn health sensors integrating low-power CMOS with microsystem technologies.^[22] In the 2010s, imec shifted toward beyond-CMOS paradigms to address silicon's physical limits, pioneering III-V compound semiconductors on silicon substrates and gate-all-around nanowire transistors, with record transconductance in III-V-on-Si devices demonstrated by 2015 through refined epitaxial growth and interface engineering.^[29] Infrastructure maturation included scaling up 300 mm wafer pilot lines—inaugurated in 2004 and expanded thereafter—for industrial-grade prototyping of advanced nodes, facilitating rapid iteration on high-volume manufacturing challenges like yield and defectivity.^[30] To tackle interconnect bottlenecks and power walls, where empirical data showed quadratic latency increases with wire length, imec validated 3D stacking via copper-to-copper hybrid bonding, achieving sub-micron pitches that reduced energy per bit by stacking logic and memory layers while preserving thermal management.^[31] Diversification accelerated with the 2010 launch of imec's Optical I/O program, driving silicon photonics integration for on-chip optical interconnects, which empirically outperformed electrical links in bandwidth-density by integrating lasers, modulators, and detectors on CMOS-compatible platforms to alleviate power dissipation in data movement.^[32] The 2016 merger with iMinds further broadened digital technology scope, incorporating expertise in high-performance computing and sensors, as evidenced by the ExaScience Lab established in 2013 for exascale simulations in healthcare applications.^[22] These developments positioned imec as a hub for causal solutions to scaling endgames, prioritizing measurable metrics like performance-per-watt over unsubstantiated sustainability narratives.

Recent Milestones (2020s)

In 2022, imec advanced high-numerical-aperture (High-NA) extreme ultraviolet (EUV) lithography in collaboration with ASML, demonstrating progress toward patterning critical features for logic chips beyond the 2 nm node with reduced steps compared to low-NA systems, addressing scaling challenges amid global semiconductor supply constraints.^[33] This initiative built on imec's infrastructure preparations for High-NA scanners, enabling denser interconnects essential for continued transistor density gains under physical limits like the von Neumann bottleneck in compute architectures. Concurrently, imec developed machine learning accelerators tailored for edge computing, optimizing energy efficiency for AI workloads in resource-constrained devices, as traditional von Neumann designs faced escalating power demands from data movement.^[34] In December 2024, imec and partners including Ghent University unveiled a shortwave infrared (SWIR) image sensor prototype using lead-free indium arsenide quantum dot photodiodes, achieving 1390 nm imaging on silicon substrates and offering an environmentally sustainable alternative to toxic lead-based detectors for applications in machine vision and sensing.^[35] This breakthrough, presented at the IEEE International Electron Devices Meeting, mitigated regulatory hurdles on hazardous materials while maintaining performance in penetrating fog or distinguishing materials indistinguishable in visible light. By March 2025, imec formalized a five-year strategic partnership with ASML to enhance semiconductor research and sustainability in Europe, focusing on sub-2 nm technologies, AI applications, and resource-efficient manufacturing processes to counter supply chain vulnerabilities and energy-intensive production scales.^[36] In May 2025, at the imec Technology Forum (ITF) World, imec demonstrated a miniaturized ingestible sensor prototype—measuring 2.1 cm by 0.75 cm—for non-invasive gut health monitoring, capable of sampling biomarkers for inflammation and microbiome analysis to support clinical studies on digestive disorders.^[37] That same month, imec CEO Luc Van Gorp advocated for reconfigurable, programmable AI chip architectures to dynamically allocate resources and overcome von Neumann inefficiencies, enabling adaptable hardware for evolving AI demands without frequent redesigns amid rapid algorithmic shifts.^[38]

Organizational Structure

Headquarters and Campuses

Imec's headquarters are located in Leuven, Belgium, where the organization maintains its primary research infrastructure, including state-of-the-art cleanrooms equipped with 200mm and 300mm pilot lines dedicated to semiconductor prototyping and testing for yield optimization and device reliability.^[39] This central facility supports core nanoelectronics activities and houses the majority of imec's workforce, with approximately 4,000 of its over 5,500 employees based there as of 2023.^[40] The Leuven site's emphasis on advanced fabrication capabilities enables focused empirical validation of process technologies, minimizing overhead while maximizing R&D throughput.^[39] Imec operates specialized campuses to address targeted technological domains, including imec the Netherlands in Eindhoven, established in 2005 through a partnership with TNO at the Holst Centre on High Tech Campus.^[22] This site integrates nanoelectronics and digital technology development, leveraging proximity to industrial ecosystems for efficient collaboration. In Spain, imec is developing a research center in Malaga, announced in 2024 via a memorandum of understanding with regional and national authorities, to host a pilot line for photonic integrated circuits.^[41] Imec's U.S. presence includes facilities in Florida at NeoCity in Kissimmee, supporting application-oriented scaling through partnerships with local universities and industry.^[42] These distributed sites optimize resource use by aligning infrastructure with regional expertise and partner needs, without diluting the core empirical focus at Leuven.^[17]

Funding and Governance Model

Imec functions as a non-profit association (vzw) under Belgian law, enabling a hybrid funding model that sustains pre-competitive research in nanoelectronics and digital technologies. In 2024, total operating income stood at €1,033.93 million, with government grants comprising €239.21 million (23.1%), including €135.09 million from the Flemish Government and additional EU and foreign contributions.^[15] The bulk originates from private industry sources: €753.31 million in turnover (72.9%) from contracts and services, plus €144.74 million (14.0%) from joint development programs, which often incorporate in-kind equipment and expertise from partners like semiconductor manufacturers.^[15] This evolution from early heavy public reliance—90% in 1984—to over 75% industry funding today diversifies revenue streams, reducing dependency on state directives and fostering collaborative innovation across value chains.^[43]^[11] Governance centers on a Board of Directors with 14 members, including delegates from industry, Flemish universities, and the regional government, alongside 64% independent directors to balance interests.^[44] The board delegates operational authority to an Executive Board led by the CEO, adhering to a Good Governance Charter that emphasizes transparency and stakeholder alignment. Intellectual property from joint projects is typically co-owned or licensed non-exclusively, with royalties—estimated at 1-2% of total revenues—reinvested into R&D, supporting sustained output like 200 patent applications in 2024. ^[15] This framework mitigates risks of single-source bias, as public funding's influence on priorities is counterbalanced by industry-driven contracts, yielding empirical successes in technology transfer evidenced by revenue growth from €680 million in 2020 to over €1 billion in 2024.^[45] ^[15] Nonetheless, the persistent government share warrants scrutiny for potential alignment with regional policy agendas over purely market needs.^[11]

Nanoelectronics and Semiconductor Research

Advanced Scaling and Lithography Techniques

Imec has pioneered advancements in extreme ultraviolet (EUV) lithography, utilizing a 13.5 nm wavelength to enable patterning at scales approaching atomic dimensions, with pilot demonstrations in the 2010s through collaborations in industry consortia.^[46] These efforts addressed fundamental challenges in resolution and throughput, constrained by the diffraction limit of light, where feature sizes below 7 nm require multi-patterning or shorter wavelengths to mitigate line-edge roughness and stochastic defects.^[47] In high-numerical-aperture (NA) EUV systems, Imec achieved key milestones for sub-2 nm nodes, including single-patterning demonstrations on 300 mm wafers starting from patterned substrates prepared ahead of ASML's 0.55 NA prototypes in 2021, enabling 20 nm pitch lines with 13 nm tip-to-tip spacing for damascene metallization by 2025.^[48]^[49] This progression supports scaling beyond 2 nm by improving depth-of-focus and reducing overlay errors, though physical limits like photon shot noise impose empirical ceilings on defectivity at densities exceeding 300 million contacts per mm².^[49] Device architectures have evolved to gate-all-around (GAA) field-effect transistors (FETs), with Imec demonstrating nanosheet-based GAA structures in the early 2020s, offering superior electrostatic control over FinFETs by fully encircling stacked silicon channels, achieving drive currents up to 410 mA/mm at 40 nm gate lengths in 2D material variants.^[50] These designs counteract short-channel effects driven by quantum confinement, where channel thicknesses below 5 nm trigger measurable tunneling currents, verified through direct measurement of subthreshold leakage in scaled prototypes.^[51] Backside power delivery networks (BSPDN), integrated with buried power rails, were experimentally validated by Imec in 2023, reducing IR drop by up to 1.7 times compared to frontside schemes through direct backside vias, enabling denser routing and lower resistance paths critical for high-performance computing at nodes below 1 nm equivalent.^[52] This addresses causal power integrity issues from increased transistor density, where frontside congestion exacerbates voltage droop exceeding 10% of supply in dense arrays.^[53] Imec's scaling roadmap projects progression to 1 nm (A10) nodes by the early 2030s, grounded in measurements of quantum tunneling probabilities that rise exponentially below 0.7 nm gate oxides, necessitating hybrid 2D/3D architectures to sustain density gains while respecting thermodynamic limits on heat dissipation and variability.^[54] Empirical data from 300 mm wafer flows confirm viability up to sub-1 nm equivalents, though ballistic transport and dopant fluctuation impose hard ceilings without novel materials like monolayer MoS₂ channels.^[55]^[56]

Emerging Architectures and Materials

IMEC has developed advanced 2.5D and 3D integration methods to extend CMOS scaling beyond planar limits, emphasizing high-density interconnects through hybrid bonding techniques. In 2021, IMEC demonstrated hybrid bonding for 3D system-on-chip (3D-SOC) architectures, achieving pitches below 1 µm, which surpass the capabilities of 2.5D microbumps and enable denser chiplet stacking for improved performance per area.^[57]^[58] These approaches leverage wafer-to-wafer or die-to-wafer bonding of copper pads and dielectrics, supporting heterogeneous stacking of logic, memory, and analog dies while maintaining thermal and electrical efficiency.^[59] For vertical transistor scaling, IMEC pursues complementary field-effect transistors (CFETs), which stack n-type and p-type FETs monolithically or sequentially to achieve significant area reduction. Introduced as a contender for nodes beyond 3 nm, CFETs offer up to 50% scaling in standard cells and SRAM, with monolithic variants providing an additional 15% area benefit through tighter n-p spacing compared to horizontal nanosheet devices.^[60]^[61] IMEC's forksheet architecture serves as an intermediate step, enhancing gate control before full CFET adoption, with demonstrations showing compatibility for sub-1 nm gate lengths.^[62] To address silicon's electron mobility limitations at advanced nodes, IMEC explores III-V compounds and 2D materials as channel alternatives. Pilot integrations of III-V materials, such as InGaAs nanowire FETs, achieved record gate-all-around performance metrics in 2015, with subsequent GaAs-based lasers fabricated on 300 mm silicon wafers via CMOS-compatible processes.^[29]^[63] For 2D semiconductors, IMEC's MoS₂ channel FETs exhibit electron mobilities exceeding 200 cm²/V·s in ultra-scaled configurations, outperforming bulk silicon in short-channel electrostatics while enabling gate lengths below 10 nm.^[64]^[65] Heterogeneous integration of these materials faces yield hurdles from thermal mismatch, defect propagation, and precision alignment, with empirical data from IMEC's pilot lines highlighting manufacturing variability as a key limiter to commercial viability.^[66] IMEC mitigates these through 300 mm CMOS pilot line demonstrations, achieving functional III-V and 2D device yields via standardized processes, though full-scale adoption requires resolving contact resistance and uniformity issues for metrics beyond lab prototypes.^[67]^[68]

Digital Technologies

Artificial Intelligence and Neuromorphic Computing

Imec has developed neuromorphic hardware architectures inspired by biological neural systems to enable energy-efficient artificial intelligence processing, particularly for edge inference tasks where power constraints dominate due to data movement overheads in conventional von Neumann architectures.^[69] These systems employ spiking neural networks (SNNs) that process asynchronous, event-driven inputs, activating computations only upon relevant stimuli, thereby minimizing constant clock-driven activity and reducing energy dissipation by orders of magnitude compared to frame-based digital neural networks.^[70] For instance, in 2021, imec fabricated an event-based SNN chip in 40 nm CMOS technology, achieving low-latency inference with power consumption in the microwatt range for sensor data classification, supporting sparsity exploitation through on-chip synaptic weight storage and local learning rules.^[71] Earlier prototypes, such as the 2020 SNN-based integrated circuit for radar signal processing, demonstrated real-time learning from data streams with energy efficiencies enabling personalized AI models at the edge, where traditional GPUs falter due to their high baseline power draw from redundant data shuffling.^[72] Imec's neuromorphic designs, akin to event-driven processors like Akida, prioritize causal efficiency by aligning hardware operations with sparse, biologically plausible signaling, addressing fundamental energy bottlenecks in AI scaling rather than relying on unsubstantiated claims of "sustainable" scaling through software optimizations alone.^[70] Empirical benchmarks show these chips delivering inference accuracies comparable to deep neural networks while consuming fractions of the power, with event-driven processing yielding up to 100-fold reductions in operations per inference for vision tasks.^[73] Complementing neuromorphic efforts, imec advances analog in-memory computing accelerators to bypass digital shuttling losses, performing matrix-vector multiplications directly in analog memory arrays for deep neural network inference. In collaboration with GLOBALFOUNDRIES, a 2020 prototype achieved 10 to 100 times higher energy efficiency than digital counterparts in benchmarks, with demonstrated throughput of 2,900 trillion operations per joule for convolutional layers.^[74]^[75] These gains stem from parallel analog computations exploiting device physics for multiplication, though precision limitations necessitate hybrid digital-analog co-designs to maintain accuracy under noise.^[76] Looking ahead, imec's CEO Luc Van den hove outlined in May 2025 a vision for programmable AI accelerators that integrate reconfigurable building blocks—such as supercells combining multiple compute paradigms—allowing hardware adaptation to evolving sparsity patterns and workload demands without full redesigns.^[38] This approach emphasizes semiconductor co-design to harness intrinsic sparsity in AI models, targeting beyond-CMOS scaling where energy per operation plateaus in pure digital paradigms, with prototypes projected to enable flexible inference engines by integrating neuromorphic elements into tiled accelerator fabrics.^[77]

Photonics and Optical Interconnects

Imec has developed silicon photonics technologies to overcome bandwidth limitations in electronic interconnects, where copper-based systems suffer from signal attenuation, crosstalk, and power inefficiencies beyond short distances, typically limiting throughput to under 100 Gbps per channel with losses exceeding 10 dB/m at high frequencies.^[32] Optical interconnects leveraging photonics enable higher bandwidth densities, targeting over 1 Tbps/mm while maintaining energy efficiency below 1 pJ/bit, as pursued in Imec's optical I/O research program.^[78] This approach integrates waveguides, modulators, and detectors on silicon substrates compatible with CMOS processes, facilitating co-integration with electronic chips for data center applications.^[79] Key advancements include Imec's iSiPP50G platform, which supports 50 Gbps non-return-to-zero (NRZ) modulation with passive devices like low-loss waveguides (propagation losses around 2.5 dB/cm) and active components such as electro-absorption modulators.^[80] Demonstrated in 2017, this platform enabled high-speed optical links for data centers by incorporating heterogeneous integration of III-V lasers and germanium photodetectors, achieving bit error rates below 10^{-12} at 50 Gbps.^[79] Subsequent scaling has focused on pulse-amplitude modulation (PAM-4) schemes, with Imec targeting 400 Gbps links by aggregating four 100 Gbps lanes, reducing optical insertion losses to under 5 dB for improved throughput in rack-scale interconnects.^[81] In co-packaged optics (CPO), Imec has demonstrated prototypes integrating photonic dies directly with electronic processors via hybrid bonding at pitches below 10 μm, minimizing latency by shortening electrical paths to under 1 mm and enabling channel rates exceeding 100 Gbps.^[82] A 2023 study highlighted scalability to 400 Gbps per lane using C-band GeSi electro-absorption modulators with bandwidths over 110 GHz, verified through eye diagrams showing clear openings at 200 Gbaud PAM-4 signaling.^[83] These efforts address data center demands for terabit-scale I/O, with pilot interconnects demonstrating end-to-end efficiencies competitive with pluggable modules but with 20-30% lower power draw.^[84] Thermal management remains a critical challenge, as photonic components generate localized heat from laser operation (up to 10 mW per channel) and modulators, exacerbating gradients in 3D-stacked configurations where silicon photonics' thermal conductivity mismatches electronics, leading to hotspots exceeding 100°C and reliability degradation via thermomigration in interconnects. Imec's modeling frameworks predict these effects in back-end-of-line (BEOL) structures, showing coupled electro-thermal simulations reveal up to 50°C differentials that necessitate advanced cooling, such as microchannel integration, to maintain performance in dense CPO setups. Empirical tests in pilot systems confirm that without mitigation, thermal crosstalk increases bit error rates by factors of 10 in multi-channel arrays.^[85]

Health and Biotechnology

Neural Interface Technologies

IMEC has developed high-density neural probes under the Neuropixels platform, enabling simultaneous recording from thousands of neurons with minimal tissue displacement. Initial Neuropixels 1.0 probes, introduced in 2017 following development starting in 2016, featured CMOS-integrated electrodes capable of 384-960 recording sites per shank, supporting sampling rates up to 30 kHz per channel for capturing extracellular action potentials and local field potentials in vivo.^[86]^[87] These probes have been implanted in rodents, nonhuman primates, and humans, yielding signal-to-noise ratios exceeding 20 dB for isolated single-unit activity, which facilitates precise spike sorting and tracking of neural dynamics across cortical layers.^[88]^[89] Updates in Neuropixels 2.0, released in 2021, increased site density to over 5,000 electrodes per probe while reducing shank dimensions to 10 μm thick and 70 μm wide, improving stability for chronic recordings lasting months in freely moving animals.^[90]^[91] The design incorporates multiplexed readout electronics and on-probe amplification, minimizing cable tethering and enabling dense sampling of neural populations spanning multiple brain regions, with verified motion correction algorithms preserving spike fidelity during behavioral tasks.^[87] Recent iterations, such as NP Ultra in 2025, achieve 1.3 sites per μm along the shank, enhancing detection of low-amplitude signals from deeper structures like the hippocampus.^[89] These probes prioritize empirical metrics like yield of well-isolated units (often >200 per insertion) over unsubstantiated therapeutic claims, supporting causal inference in neuroscience through high-fidelity data.^[92] Complementing in vivo tools, IMEC's CMOS-based multi-electrode arrays (MEAs) interface with brain organoids for in vitro neural circuit analysis, integrating thousands of electrodes in under 1 mm² for high-resolution extracellular recording and stimulation.^[93] These systems, advanced since 2020, support closed-loop paradigms where detected spikes trigger optogenetic or electrical feedback, enabling causal probing of network dynamics in organoid models of human brain tissue.^[94] By 2025, collaborations have embedded organoids on silicon substrates with microfluidic perfusion, achieving sub-cellular resolution for studying disease mechanisms like Parkinson's without relying on animal models.^[95] Such platforms emphasize verifiable signal quality, with noise floors below 10 μV RMS, to ground interpretations in direct electrophysiological evidence rather than inferred behaviors.^[96]

Diagnostic and Wearable Devices

IMEC has collaborated with miDiagnostics on point-of-care diagnostic platforms utilizing silicon chip technology for capillary blood analysis, enabling complete blood counts (CBC) from microliter drops without centrifugation.^[97] This approach leverages nanofluidic processors and capillary forces to process samples rapidly, with prototypes tested in microgravity environments via NASA funding in 2019 to validate performance under extreme conditions.^[98] The technology aims for lab-equivalent accuracy in detecting cells and proteins, supporting decentralized testing beyond traditional venipuncture.^[99] In breath-based diagnostics, IMEC developed a patented sampler chip that captures exhaled aerosols for biomarker detection, licensed to miDiagnostics in 2021 for commercialization as a rapid COVID-19 breathalyzer alternative to nasopharyngeal swabs.^[100] The device uses standard semiconductor fabrication to analyze volatile organic compounds (VOCs) and viral particles in breath, offering potential for non-invasive screening of respiratory diseases with results comparable to PCR in sensitivity and specificity during clinical evaluations of similar breath technologies.^[101]^[102] For wearable monitoring, IMEC's disposable patches integrate sub-10 nA sensitivity biopotential readouts for electrocardiogram (ECG) and galvanic skin response (GSR) via the Museic V2 platform, supporting real-time vital sign tracking with Bluetooth Low Energy connectivity.^[103] These flexible, skin-conformable designs, developed since 2008, achieve 99.93% QRS detection sensitivity across over 86,000 beats in validation datasets, outperforming rigid sensors in ambulatory settings while minimizing power consumption for extended wear.^[104] Edge processing enables on-device analysis of ECG waveforms and activity via integrated accelerometers, prioritizing signal fidelity over battery life trade-offs in prototypes like the 2019 health patch.^[105]^[106]

Biosensing and Precision Medicine

Imec develops biosensing technologies that enable molecular-level detection of biomarkers, leveraging CMOS-integrated microfluidics and solid-state nanopores to achieve high sensitivity and throughput for precision medicine applications. These platforms facilitate rapid analysis of biological fluids, such as blood or gastrointestinal contents, by combining electrical, photonic, and nanofluidic sensing mechanisms with on-chip processing. For instance, solid-state nanopores allow single-molecule resolution for DNA sequencing and protein detection, addressing limitations in traditional methods by enabling long-read sequencing and proteomics at reduced costs.^[107]^[108]^[109] A key advancement in gut-related biosensing is Imec's prototype ingestible sensor, demonstrated at the Imec Technology Forum (ITF) World 2025, which measures 2.1 cm in length and 0.75 cm in diameter—three times smaller than comparable capsules. This device monitors redox balance, pH, and temperature along the gastrointestinal tract to assess intestinal inflammation and microbiome composition, providing non-invasive data grounded in biochemical kinetics for early disease detection. By sampling gut contents in real-time, it supports precision interventions tailored to individual metabolic profiles, with prototypes validated for clinical studies through partnerships like OnePlanet Research Center.^[37]^[110]^[111] Lab-on-chip systems further exemplify Imec's biomarker detection capabilities, integrating nanofluidics with CMOS for continuous electrochemical sensing and polymerase chain reaction (PCR) amplification. These chips accelerate biomarker identification, such as viral DNA or proteins, by miniaturizing fluid handling to nanoliter scales, where diffusion-limited reaction rates are mitigated through precise control of flow velocities and surface interactions—achieving detection times reduced to minutes compared to benchtop assays. Collaborations, including with Janssen Pharmaceutica, target fluid scanning for diseases like infections, yielding results in fractions of conventional lab times while maintaining analytical accuracy.^[112]^[113]^[114] Integration with genomics leverages CMOS-compatible nanopore arrays for single-cell and single-molecule sequencing pilots, as advanced in 2024 efforts toward scalable proteomics. These systems employ bio-FinFETs and silicon nitride photonics to readout translocation events, overcoming diffusion bottlenecks by engineering pore geometries and applying controlled voltages, which enhance capture rates and signal-to-noise ratios for rare variants or low-abundance analytes. Such causal enhancements in nanofluidic confinement enable high-throughput analysis, supporting personalized medicine by linking genomic data to functional protein kinetics without reliance on amplification biases.^[108]^[109]^[115]

Energy and Sustainability

Photovoltaics and Energy Harvesting

Imec's photovoltaic research emphasizes tandem architectures to overcome efficiency limitations of single-junction silicon cells, which are constrained by the Shockley-Queisser limit of approximately 29%. By stacking perovskite top cells with established bottom cells like silicon or copper indium gallium selenide (CIGS), imec has demonstrated power conversion efficiencies exceeding those of standalone silicon devices. For instance, a perovskite-silicon tandem achieved 27.1% efficiency, surpassing the best monocrystalline silicon cells at the time.^[116] Similarly, perovskite-CIGS tandems reached 24.6% efficiency, leveraging the complementary absorption spectra of the materials to capture a broader range of sunlight.^[117] Recent advancements include inverted perovskite cells with 24.3% efficiency, incorporating dual-layer passivation to reduce defects and improve charge extraction. In 2024, imec reported perovskite-on-CIGS tandems with efficiencies near 30% for small-area cells and 21% for larger modules, highlighting progress toward scalable thin-film production on flexible substrates. These configurations prioritize manufacturing compatibility, such as ultrasonic spray coating for uniform perovskite layers, to bridge lab-scale records with industrial yields. However, efficiency gains plateau without addressing recombination losses at interfaces, where empirical data shows voltage deficits persisting despite optimized bandgaps.^[118]^[119] Stability remains a critical empirical barrier, as perovskites exhibit degradation under humidity and oxygen exposure, leading to phase instability and ion migration. Imec's outdoor testing of perovskite modules under real-world Mediterranean conditions demonstrated 78% power retention after one year, with initial burn-in losses of 7-8% per month stabilizing thereafter. Encapsulation strategies and molecular interface treatments, such as ammonium salts, have extended operational lifetimes, but achieving a mean time to failure exceeding 10 years requires further validation beyond accelerated aging tests. Thin-film perovskites and organics are explored for low-power energy harvesting in IoT devices, where ambient light yields suffice for sensors, though intermittent solar input demands high specific power and robustness over continuous illumination scenarios. Scalable yields for modules lag lab cells due to uniformity issues in deposition, underscoring the need for process controls to realize cost-effective harvesting without relying on narrative-driven projections of rapid commercialization.^[120]^[121]^[119]

Battery and Power Management Innovations

IMEC researchers have pioneered solid-state microbatteries employing lithium-metal anodes and ceramic-based solid electrolytes to deliver micro-scale energy storage with enhanced safety and energy density for applications in wearables and medical implants.^[122] These batteries replace liquid electrolytes with solids, mitigating risks of leakage and thermal runaway while supporting higher volumetric capacities suitable for integration into compact CMOS-compatible systems.^[122] A key advancement occurred in September 2024, when IMEC unveiled a lithium-metal solid-state battery prototype achieving 1070 Wh/L energy density—33% higher than the 800 Wh/L typical of advanced lithium-ion cells—via a scalable manufacturing process using cost-effective halide solid electrolytes and thin-film deposition techniques.^[123] This design targets cycle lives exceeding those of conventional microbatteries by minimizing dendrite formation and interface degradation, with initial testing showing stable performance over hundreds of cycles under high-rate discharge.^[123] Earlier efforts, including the 2022 spin-off of SOLiTHOR, focused on disruptive solid-state cells with improved ionic conductivity and compatibility for CMOS backend integration, enabling on-chip power for low-profile wearables.^[124] In power management, IMEC integrates thin-film sensors directly into battery structures to support advanced battery management systems (BMS), providing in-situ measurements of state-of-charge, temperature, and strain for real-time optimization and early degradation detection.^[122] These sensors facilitate data-driven models derived from accelerated stress testing, correlating factors like elevated temperature and cycling rates to capacity fade mechanisms such as solid-electrolyte interphase growth, thereby predicting long-term cycle life with reduced reliance on extended real-world validation.^[122] For ultra-low-power regimes, IMEC's complementary work on efficient DC-DC conversion in integrated circuits achieves over 90% efficiency at sub-mW loads, minimizing quiescent power draw in battery-powered IoT and wearable nodes.^[125]

Sensing and Imaging Systems

Image Sensors and Vision Applications

Imec develops CMOS image sensors optimized for high quantum efficiency and low noise, prioritizing fundamental performance metrics over integrated processing features to enable reliable vision applications in demanding environments. These sensors leverage advanced pixel architectures, such as pinned photodiodes and backside illumination, to achieve quantum efficiencies exceeding 90% across the visible spectrum without color filters, facilitating superior light capture for low-illumination scenarios.^[126] Noise performance in prototypes targets ultra-low read-out levels, with demonstrations as low as 6.1 electrons in thin-film variants adaptable to visible detection, though analog time-delay-integration (TDI) imagers achieve around 20 electrons RMS under high-speed conditions.^[127]^[126] Advancements in global shutter technology trace back to Imec's early work through spin-offs like FillFactory, which pioneered CMOS global shutter pixels in the early 2000s, with further refinements in the 2010s via cmosis for machine vision. These sensors eliminate rolling shutter distortions, enabling distortion-free capture at high frame rates suitable for industrial inspection and motion analysis. Imec's high-speed prototypes have demonstrated imaging at up to 326,000 frames per second, supporting applications requiring precise temporal resolution without motion artifacts.^[128]^[129]^[130] For high dynamic range (HDR) imaging, Imec employs hybrid CCD-in-CMOS stacking, integrating charge-coupled device pixels with CMOS readout circuitry on a single chip using 130 nm processes. This approach yields digital TDI sensors with over 60 dB dynamic range, combining the charge transfer efficiency of CCDs with CMOS scalability for vision systems handling extreme contrast. Such designs enhance HDR performance in stacked configurations, outperforming traditional CMOS in signal fidelity while maintaining compact form factors.^[126]^[131] In automotive advanced driver assistance systems (ADAS), Imec's CMOS sensors contribute to vision-based perception through high quantum efficiency enabling low-light operation, with efficiencies supporting detection thresholds below typical ambient conditions. These sensors integrate into multi-sensor fusion for obstacle detection and environmental mapping, emphasizing raw imaging fidelity to reduce reliance on computational corrections. Prototypes exhibit noise floors conducive to reliable night-time performance, aligning with ADAS requirements for minimal false positives in varied lighting.^[126]^[132]^[127]

Specialized Detectors (e.g., SWIR)

Imec researches short-wave infrared (SWIR) detectors as alternatives to costly indium gallium arsenide (InGaAs) devices, employing colloidal quantum dots (CQDs) for solution-processable fabrication and tunable bandgap absorption via size-controlled synthesis, which enables cost-effective extension into the 1–1.7 μm range without epitaxial growth limitations.^[35]^[133] In the Belgian Q-COMIRSE project, completed in 2024, imec integrated lead-free indium arsenide (InAs) CQD photodiodes into a prototype SWIR sensor, achieving functional imaging at 1390 nm on both glass and silicon substrates as an environmentally sustainable substitute for lead-based PbS or PbSe QDs.^[35]^[134] This approach leverages the flexibility of thin-film CQD layers, compatible with large-area printing, to support industrial hyperspectral sorting and defect detection where InGaAs scalability is prohibitive.^[135]^[136] Bandgap engineering in InAs CQDs allows precise spectral cutoff tuning by adjusting particle diameter from 3–5 nm, optimizing quantum yield for SWIR responsivity while minimizing dark current through ligand passivation and heterojunction designs with wide-bandgap transport layers.^[35]^[137] Imec's monolithic thin-film SWIR sensors have demonstrated pixel densities up to 1.82 μm pitch, surpassing hybrid InGaAs-CMOS limits for compact, high-resolution modules in machine vision.^[138] Integration of pinned photodiode structures in CQD thin films further reduces noise and improves charge collection efficiency, enabling operation in ambient conditions for applications like plastic recycling identification via overtone absorption bands.^[139]^[140] These advancements prioritize causal material innovations over substrate constraints, yielding detectors with broadband sensitivity from visible to SWIR in devices like the Acuros camera (400–1700 nm).^[133]

Applications in Mobility and Urban Systems

Automotive and Sustainable Transport

Imec has developed gallium nitride (GaN)-on-silicon power devices tailored for electric vehicle (EV) powertrains, emphasizing enhanced efficiency and reliability in high-voltage applications. These devices leverage GaN's superior electron mobility to enable faster switching speeds and reduced energy losses compared to traditional silicon counterparts, supporting compact inverters and converters in EVs.^[141] Imec's research includes detailed analysis of failure mechanisms under power cycling, achieving breakdown voltages exceeding 1200 V on 200 mm wafers, which positions GaN as a cost-effective alternative to silicon carbide (SiC) for automotive traction systems.^[142] In parallel, imec advances silicon carbide (SiC) and GaN integration for power electronics, as highlighted in collaborative webinars and programs focusing on automotive-grade modules capable of handling high thermal loads. These wide-bandgap semiconductors undergo rigorous qualification for EV inverters, prioritizing metrics like on-resistance and thermal management over regulatory emission thresholds, with demonstrated efficiencies enabling smaller, lighter powertrain components.^[143] Imec's 300 mm GaN program, launched in 2025, further scales production for low- and high-voltage devices, reducing manufacturing costs while maintaining automotive reliability standards.^[144] For advanced driver-assistance systems (ADAS) and autonomy, imec integrates radar and LiDAR sensors using compact semiconductor solutions. High-resolution 140 GHz radar chips provide precise object detection with sub-millimeter accuracy, suitable for integration into vehicle bumpers without compromising aerodynamics, and are projected for commercial deployment by the early 2030s following power and signal optimization.^[145] Complementary on-chip LiDAR prototypes employ photonic integration for solid-state scanning, enhancing environmental perception in adverse weather where traditional mechanical systems falter.^[146] Imec's distributed photonics-based 144 GHz radar, demonstrated in 2025, fuses radar data with LiDAR inputs via code-division multiplexing, improving resolution for collision avoidance.^[147] Edge AI architectures from imec enable real-time processing for autonomous driving, minimizing latency through on-chip inference to support instant decision-making in dynamic environments. These systems process sensor fusion data locally, reducing reliance on cloud connectivity and achieving response times critical for safety, as validated in ADAS prototypes mitigating human error scenarios.^[148] Simulations of edge AI workloads in imec's frameworks demonstrate latencies under 1 ms for perception tasks, outperforming centralized models by orders of magnitude in bandwidth-constrained vehicular settings.^[149] Reliability testing underscores imec's focus on empirical durability, with GaN and SiC devices subjected to thermal cycling from -40°C to 150°C to replicate automotive extremes like engine bay heat and cold starts. These tests quantify degradation in power modules, revealing interface failures under sequential stresses and informing design iterations for zero-defect operation over 15-year lifespans.^[150] Imec's ITF presentations in 2024 and 2025 emphasized such data-driven validation for sustainable transport semis, prioritizing cycle counts and failure rates over idealized efficiency projections.^[151]

Smart City Infrastructures

Imec has developed distributed IoT sensor networks to enhance urban efficiency, particularly through its City of Things initiative launched in Antwerp in 2017, which serves as a living lab for scalable deployment of sensing technologies in real-world urban environments.^[152]^[153] These networks integrate low-power sensors for monitoring traffic flows and energy consumption, enabling data-driven optimizations such as dynamic traffic signal adjustments and predictive energy distribution in municipal grids. For instance, in pilot deployments, IoT meshes using Bluetooth Low Energy (BLE) variants have supported energy-efficient lighting systems that adapt to real-time usage patterns, reducing overall municipal power draw by integrating with broader grid management.^[154] Scalability is achieved via open architectures that standardize data notation for machine-interpretable queries, facilitating geo-temporal analysis of sensor feeds across city-scale deployments.^[155] To handle the high data volumes from these distributed sensors, imec incorporates photonic technologies for backhaul connectivity, including silicon photonics components designed for high-bandwidth, low-latency links in urban networks.^[156] These enable seamless expansion of communication infrastructure, such as 60 GHz millimeter-wave solutions for rapid bandwidth scaling in dense areas, supporting the aggregation of IoT data without bottlenecks. Edge processing further minimizes latency by performing computations locally on devices, as demonstrated in imec's collaborations yielding AI-optimized chips that execute deep neural networks on resource-constrained IoT nodes, achieving sub-millisecond response times in Antwerp's digital twin simulations for urban planning.^[157]^[158] In pilot cities like Antwerp, this approach has reduced end-to-end data processing delays by distributing intelligence to the network periphery, allowing for real-time interventions in energy and traffic systems.^[159] Despite these advances, deploying such infrastructures raises causal challenges in data flows, including privacy risks from pervasive sensing and security vulnerabilities in interconnected IoT ecosystems. Imec addresses these through hardware-secured sensors incorporating cryptography chips for low-power devices, yet systemic dependencies on centralized data aggregation can expose networks to breaches if edge safeguards fail.^[160] Scalability in diverse urban settings remains constrained by interoperability standards and the need for robust encryption to prevent unauthorized access to causal inference models derived from aggregated sensor data.^[161]

Partnerships, Impact, and Commercialization

Industry Collaborations and Spin-Offs

Imec maintains extensive industry partnerships to facilitate technology transfer and commercialization of its nanoelectronics research. A notable collaboration is the five-year strategic partnership agreement signed with ASML in March 2025, which provides imec access to ASML's full lithography portfolio, including 0.55 NA EUV and DUV immersion systems, to advance semiconductor research and sustainable manufacturing practices in Europe.^[36] Similarly, imec collaborates with TSMC on beyond-CMOS platforms and process development for advanced nodes, enabling validation of imec-developed technologies in high-performance applications through joint CMORE initiatives.^[162] These ties, involving equipment sharing and co-development, have supported imec's role in prototyping and scaling innovations for partners' production lines. Imec has generated over 100 spin-off companies since 1986, leveraging its intellectual property to commercialize specialized technologies. Examples include Vertical Compute, launched in 2025 to address AI compute-memory bottlenecks with 3D-stacked processors and raising €20 million in funding, and Axithra, a 2023 spin-off focused on high-resolution 3D imaging sensors that secured €10 million for R&D in photonics applications.^[11]^[163]^[164] Other spin-offs, such as those specializing in analog ICs like ICsense for high-precision sensors, demonstrate imec's emphasis on niche markets including automotive and health tech. This spin-off ecosystem has accelerated the transfer of imec's patents—numbering over 1,600 families—into market-ready products, with many co-owned by industry partners to ensure rapid adoption.^[19]^[165] These collaborations and spin-offs have bolstered Europe's semiconductor technological base, particularly in response to supply chain vulnerabilities highlighted by the 2022 EU Chips Act, which imec supports through coordinated design platforms and pilot lines for advanced nodes.^[166] By enabling joint R&D and IP licensing, imec's model has contributed to enhanced EU capabilities in logic scaling and specialized devices, reducing reliance on non-European manufacturing while fostering economic returns via licensed technologies and venture-backed ventures.^[11]

Economic and Technological Influence

Imec's collaborative R&D consortia enable industry participants to pool resources, significantly reducing individual costs for advanced semiconductor development. By sharing access to imec's infrastructure and expertise, partners avoid duplicative investments in high-risk, capital-intensive research, with estimates indicating that such models multiply economic returns through shared innovation diffusion rather than isolated efforts. For instance, imec's programs have facilitated cost efficiencies in nanoelectronics scaling, where consortium participation lowers per-partner R&D expenditures by distributing expenses across multiple entities.^[11] Technologically, imec has exerted influence on global semiconductor trajectories, notably through its pivotal role in the extreme ultraviolet (EUV) lithography ecosystem. In partnership with ASML, imec's joint High-NA EUV lab, established in 2024, has achieved milestones in single-patterning processes, enabling denser chip architectures critical for sub-2nm nodes and contributing to the broader adoption of EUV technologies that underpin high-performance computing. Imec's research also aligns with and informs international scaling roadmaps, such as those succeeding the ITRS, by validating pathways for interconnects, materials, and metrology that guide industry planning toward continued transistor density improvements.^[167]^[49] Economically, imec's spin-off ecosystem has generated substantial employment and value addition, with over 100 ventures emerging since 1986 that leverage its IP to commercialize technologies in areas like photonics and sensors. These spin-offs, combined with imec's direct operations employing more than 5,500 researchers, contribute to Flanders' high-tech cluster, yielding an economic multiplier effect where each euro of public investment reportedly generates eleven times in broader impact, including job creation and fiscal returns. However, this influence stems partly from heavy reliance on subsidies, with public funding from Flemish, Belgian, and EU sources—such as the €2.5 billion allocated under the European Chips Act in 2024—comprising a core portion of its budget, raising questions about sustainability absent ongoing governmental support.^[19]^[12]^[168]^[169]

Challenges and Criticisms

Technical and Scaling Limitations

As semiconductor nodes approach and fall below 2 nm, imec's research highlights fundamental quantum mechanical effects, including increased electron tunneling and variability in device characteristics due to atomic-scale dimensions. These effects exacerbate short-channel control issues, where gate lengths below 5 nm lead to degraded electrostatic integrity and higher leakage currents, necessitating advanced architectures like gate-all-around (GAA) transistors and complementary field-effect transistors (CFET).^[170]^[171] Extreme ultraviolet (EUV) lithography introduces stochastic variability at these scales, manifesting as random photon-shot noise and photon blur, which result in line-edge roughness, critical dimension variability, and defects such as microbridges or missing contacts. Imec's yield models incorporate these stochastics, projecting resolution gaps that limit manufacturability below 10 nm half-pitch, with experimental validations showing orders-of-magnitude reductions in failures via stochastic-aware optical proximity correction (OPC), though residual variability persists in high-density patterns like SRAM.^[172]^[173]^[174] The breakdown of Dennard scaling compounds power delivery and thermal management challenges, with transistor density gains outpacing voltage reductions, leading to rising thermal design power (TDP) densities that exceed practical cooling limits. Imec notes that 3D stacking, while extending scaling through vertical integration, imperfectly addresses these power walls, introducing 10-30% thermal penalties in backside power delivery schemes and complicating heat extraction in dense CFET structures.^[55]^[175] Yield limitations in pilot fabrications further hinder scaling, particularly for GAA and forksheet devices, where nanosheet thinning to 4 nm or below induces fabrication complexities like channel strain loss and interface defects, often resulting in yields below 70% in early demonstrations due to etch variability and alignment errors. Imec's explorations of 2D materials aim to mitigate these, but integration challenges, including uniform deposition and contact resistance, persist, delaying high-volume manufacturability.^[176]^[50]^[56]

Funding Dependencies and Geopolitical Factors

Imec's funding model depends substantially on public sources, with approximately 75% of its budget derived from private sector contracts and the remainder from government grants and subsidized projects. In 2024, the Flemish government provided a structural grant of €135.09 million, supplemented by €89.27 million in funded projects, against a total revenue of €1.034 billion.^[15]^[14] This public component, while enabling long-term R&D infrastructure, exposes imec to fiscal policy fluctuations; for instance, Flemish subsidies have declined from over 50% of revenue in the 1980s to around 15% today, yet cuts could strain core operations amid competing regional priorities.^[177] EU-level funding, including €1.45 billion allocated under Horizon Europe and Digital Europe programmes in 2024, further ties imec's agenda to supranational directives such as the European Chips Act, which prioritizes supply chain resilience and sustainability over unrestricted pursuit of computational scaling.^[12] These mandates risk diverting resources toward politically favored areas like energy-efficient technologies, potentially at the expense of raw performance gains in logic scaling, as evidenced by the Act's emphasis on "secure and sustainable" semiconductor ecosystems rather than pure technological frontiers.^[166] Critics, including industry analysts, argue that such interventions introduce bureaucratic overhead and misaligned incentives, contrasting with more market-driven U.S. models.^[11] Geopolitically, imec's reliance on global supply chains for lithography tools and materials amplifies vulnerabilities from U.S.-China tensions, including export controls on advanced equipment that could restrict access to dual-use technologies essential for sub-2nm R&D.^[11] While imec's European headquarters mitigates some restrictions, its U.S. facilities—such as imec.usa in Albany—facilitate collaboration with American firms but heighten intellectual property exposure under U.S. regulations like the CHIPS Act's domestic content requirements and potential national security reviews. Rare instances of IP disputes have arisen in international partnerships, but imec's consortia model, emphasizing shared foreground IP, has proven resilient; nonetheless, subsidy reductions or escalated trade barriers could exacerbate these risks without diversified private revenue streams.^[178]

References

[1]
FACT SHEET: World Leaders Launch a Landmark India-Middle East ...
Sep 9, 2023 · ... European Union announced a Memorandum of Understanding committing to work together to develop a new India-Middle East-Europe Economic Corridor.
[2]
India-Middle East-Europe Economic Corridor (IMEC)
The India-Middle East-Europe Economic Corridor (IMEC) is a visionary initiative reshaping global trade, connectivity, and cooperation across three continents.
[3]
Partnership for Global Infrastructure and Investment (PGII) & India ...
Sep 9, 2023 · Partnership for Global Infrastructure and Investment (PGII) & India-Middle East-Europe Economic Corridor (IMEC). September 09, 2023. Prime ...
[4]
Memorandum of Understanding on the Principles of an India
Sep 9, 2023 · The IMEC is expected to stimulate economic development through enhanced connectivity and economic integration between Asia, the Arabian Gulf, and Europe.
[5]
The India-Middle East-Europe Economic Corridor: Connectivity in an ...
Aug 27, 2025 · The corridor would have the capacity to move about forty-six trains daily carrying 1.5 million storage containers (TEUs) annually · The IMEC ...
[6]
The infinite connection: How to make the India-Middle East-Europe ...
Apr 23, 2024 · With IMEC, the US and the EU aim to draw India closer and counter Chinese influence. The corridor would provide a boost to India's strategy to ...
[7]
IMEC's Comeback | German Marshall Fund of the United States
Apr 11, 2025 · IMEC has enjoyed bipartisan support as a mammoth geo-economic project to counter Chinese influence in Asia and the Middle East.
[8]
About imec
Imec was founded in 1984 and is today the world's largest independent research and innovation center for nanoelectronics and digital technology.Missing: scope | Show results with:scope
[9]
imec: The Semiconductor Watering Hole - The Asianometry Newsletter
Nov 9, 2022 · imec's stated mission was "to perform R&D, ahead of industrial needs by 3 to 10 years". Mostly in microelectronics and design, but later ...
[10]
Collaborative research | imec
The answer is precompetitive research: sharing expertise and research among partners across the value chain. Lowering risks and costs for everyone involved ...
[11]
Understanding imec: The Global Center for Cooperative Research ...
Mar 19, 2024 · It is the leading cooperative research center in Europe, and arguably in the world. It's based in Leuven in Belgium.
[12]
Imec in 2024: an overview
Dec 19, 2024 · World-leading in nanoelectronics R&D; Advancing semiconductor and system scaling; Advancing quantum and superconducting computing; Advancing ...<|separator|>
[13]
Imec, a world-leading research and innovation hub in ...
Feb 25, 2025 · We are proud to partner with top European research institutes CEA-Leti, Fraunhofer, VTT, CSSNT-UPB, and Tyndall for the NanoIC pilot line.
[14]
Press kit | imec
Imec leverages its state-of-the-art R&D infrastructure and its team of more than 6.000 employees ... Imec is headquartered in Leuven (Belgium), and has research ...
[15]
[PDF] Annual & sustainability report - imec corporate
Apr 25, 2025 · What did imec do in 2024? • In 2024, 528 Belgian employees bought additional holidays with their year-end bonus. • Imec changed its external ...<|separator|>
[16]
Connect with us - imec Leuven (Headquarters)
The imec headquarters are located in Leuven. It's the place where the imec story started in 1984. This is the biggest campus of imec, consisting of five ...Missing: global | Show results with:global
[17]
Imec USA: accelerating semiconductor innovation
Imec is the world's leading non-profit semiconductor research center. Since its foundation in 1984, it has operated pre-competitive research and IP licensing ...Imec Boston office · Imec's Florida center · Imec USA event calendar
[18]
European technology leader imec opens innovation hub at Purdue
Dec 11, 2023 · The Purdue location represents imec's first Midwest research office, adding to its offices in California and Florida. With imec and IEDC's ...<|separator|>
[19]
Imec spin-offs
Imec has a long history of launching start-ups and supporting innovative ideas. Here you can find a list of imec spin-offs since 1986.
[20]
[PDF] Belgium's Role in Europe's Technological Sovereignty
May 21, 2025 · Over 75% of imec's annual US$ 1 billion budget is funded directly by the private sector, reflecting the high level of trust and reliance the ...
[21]
A grain of sand, a world of hope - IMEC
Dec 20, 2024 · And, over the past forty years, we have launched more than 130 spin-offs and supported over 300 start-ups, securing nearly 1 billion euros in ...
[22]
History - IMEC
In 1984, imec was an emerging lab with a starting grant and a steep ambition. Substantial investments in infrastructure were part of imec's strategy from the ...
[23]
Does Europe have any magic left?
Feb 20, 2023 · imec's business and financing model enables it to be a neutral provider of R&D services in the semiconductor industry, which is otherwise ...<|control11|><|separator|>
[24]
What is the background of IMEC that was all over the news yesterday?
Oct 20, 2018 · In 1984, IMEC selected two CMOS process modules, wet cleaning and silicide, for research. Subsequently, it added modules required for the ...
[25]
[PDF] IP Models to Orchestrate Innovation Ecosystems:
This type of research focuses on topics that are 2-3 years ahead of market applications and is based on bilateral collaboration between an IAP partner and IMEC.
[26]
[PDF] Cmos Scaling: Present, Past and Future
Dec 10, 2024 · By the late 1990s, the limit was thought to be 0.25 µm due to increasing source/drain resistance, direct- tunneling leakage in gate oxides, and ...
[27]
[PDF] NEWSLETTER 45 - Probo
IMEC demonstrated functional amplifiers and oscillators from the first test chip of the (sub-)45nm analog/RF-CMOS program. With these results, the program is on ...Missing: 1980s | Show results with:1980s
[28]
IMEC Details 45nm Transistor R&D - EDN Network
Jun 14, 2005 · Belgian R&D center IMEC said today that it has reached several breakthroughs in gate stack technologies and multiple gate field effect ...
[29]
Imec Boosts Performance of Beyond-Silicon Devices
Dec 9, 2015 · III-V-on-Si GAA devices with a record peak transconductance at 0.5V has been achieved by optimizing both the channel epitaxy quality and the ...Missing: 2010s | Show results with:2010s
[30]
IMEC opens research-scale 300-mm wafer fab - EE Times
LEUVEN, Belgium -- IMEC, an independent research organization based here, inaugurated a 300-mm wafer fab Friday (May 7) that is aimed at helping a drive.
[31]
3D integration: IC stacking to extend scaling - IMEC
One way to further scale ICs and add more functionality per area, is to integrate circuits on top of each other, leveraging 2.5D or 3D connectivity.
[32]
How silicon photonics technology can address the networking ...
Apr 17, 2023 · “Since the start of the Optical I/O program in 2010, imec has acquired a wealth of know-how in developing silicon integrated photonics, thereby ...
[33]
High-NA EUV Patterning Ecosystem ramps up - IMEC
Apr 25, 2022 · High-NA EUV lithography is projected to print the most critical features needed for beyond 2nm logic chips with fewer patterning steps compared to current 0.33 ...Missing: demo | Show results with:demo
[34]
Machine learning accelerators - IMEC
Learn about the ways imec researchers are looking to enable more efficient machine learning in edge computing devices.Missing: 2020-2023 | Show results with:2020-2023
[35]
SWIR sensor with lead-free quantum dot photodiodes - IMEC
Dec 16, 2024 · The sensor demonstrated successful 1390 nm imaging results, offering an environmentally friendly alternative to first-generation quantum dots that contain lead.
[36]
ASML and imec sign strategic partnership agreement to support ...
ASML and imec sign strategic partnership agreement to support semiconductor research and sustainable innovation in Europe. Press release ...
[37]
Imec presents prototype of ingestible sensor for gut health monitoring
May 19, 2025 · The ingestible sensor measures redox balance, pH, and temperature, providing insights into inflammation, the gut microbiome, and overall health ...
[38]
Top semiconductor lab imec eyes 'programmable' AI chips, CEO says
May 19, 2025 · The CEO of imec, one of the world's top semiconductor R&D firms, has said the industry needs to steer towards reconfigurable chip architectures.
[39]
Infrastructure: semiconductor cleanrooms and labs - Leuven - IMEC
Explore imec's state-of-the art R&D infrastructure, including a 200mm and 300 semiconductor cleanroom and several advanced laboratories.
[40]
Research centre imec expects to hire 2,000 new employees by 2035
Nov 23, 2023 · Currently, almost 4,000 of its more than 5,500 employees work in Leuven. The growth projections include the construction of several office ...Missing: percentage | Show results with:percentage
[41]
Spanish government, region of Andalusia and imec sign MoU
Mar 13, 2024 · They have signed a Memorandum of Understanding (MoU) outlining their intent to establish a specialized chip technology pilot line in Malaga (Andalusia).Missing: 2017 | Show results with:2017
[42]
imec | LinkedIn
imec. Research Services. Imec is a world-leading R&D and innovation hub in nanoelectronics and digital technologies. See jobs Follow.
[43]
How to Make the NSTC a Moonshot Success | IFP
Apr 22, 2024 · The consortium's first year in 1984 posted 90% public funding, falling to 50% in 1992, and close to its present-day levels at 20% by 2004.<|separator|>
[44]
Board of Directors | imec
IMEC's board includes Michel Akkermans, Brigitte Boone, Ann Caluwaerts, Lieven Danneels, Marc Decramer, Ingrid De Poorter, Antoon De Proft (Chairman), Gerard ...Missing: governance | Show results with:governance
[45]
IMEC - Wikipedia
IMEC is an international research & development organization, active in the fields of nanoelectronics and digital technologies with headquarters in Belgium.
[46]
[PDF] 2020 - IMEC
Jun 16, 2021 · In 2020, 161 new patent applications were submitted and up to 1,866 scientific papers were published by imec researchers in leading journals ...
[47]
EUV Extreme Ultraviolet Lithography Wiki - SemiWiki
Jul 12, 2025 · Wavelength: 13.5 nm (compared to 193 nm in ArF DUV systems). Source ; 2000s: EUV championed by industry consortia (e.g., SEMATECH, IMEC). 2010 ...
[48]
High-NA EUV lithography: the next step after EUVL - IMEC
Oct 4, 2021 · High-NA EUV lithography is a next-generation technology using a 13.5nm wavelength, moving from 0.33NA to 0.55NA, aiming to advance Moore's Law ...<|control11|><|separator|>
[49]
2021 in 14 highlights | imec
Jan 3, 2022 · And to provide patterned 300mm wafers for process development before the first 0.55 high-NA EXE5000 prototype from ASML becomes available. Fig 1 ...
[50]
Imec achieves new milestones in single patterning High NA EUV
Sep 22, 2025 · Imec demonstrates line structures at 20nm pitch with 13nm tip-to-tip dimensions relevant for damascene metallization, as well as 20nm and ...Missing: 2022 | Show results with:2022
[51]
Outer wall forksheet: bridging nanosheet and CFET - IMEC
Jun 11, 2025 · In addition to area scaling, GAA nanosheet transistors offer another advantage over FinFETs: the gate surrounds the conduction channels on all ...
[52]
[PDF] CMOS Device Scaling by Nanosheet Channel Architectures and ...
Nanosheet architectures have several advantages as compared to FinFETs: 1) wider channel width/footprint due to stacked nanosheet channels, 2) better.
[53]
Backside power delivery options: a DTCO study - IMEC
Aug 28, 2023 · ... 2023). Researchers established a maximum allowable power loss of 35mV for the IR drop evaluation, corresponding to 10% of the nominal ...
[54]
Backside power delivery | imec
Nov 25, 2022 · On-chip power heat maps showed that BPRs with frontside power delivery could reduce the IR drop by ~1.7x compared to traditional frontside power ...
[55]
Imec Reveals Sub-1nm Transistor Roadmap, 3D-Stacked CMOS 2.0 ...
May 26, 2023 · The roadmap gives us an idea of the timelines through 2036 for the next major process nodes and transistor architectures the company will research and develop ...<|separator|>
[56]
Smaller, better, faster: imec presents chip scaling roadmap
Feb 2, 2023 · We need improved high-performance semiconductor technology. In order to achieve that, we need to address five challenges simultaneously.
[57]
Introducing 2D-material based devices in the logic scaling roadmap
Jan 16, 2025 · At 2024 VLSI, imec has demonstrated a 300mm MX2 dry transfer process flow which resulted for the first time in a repeatable process with ...
[58]
3D-SOC design and backside interconnects - IMEC
Dec 11, 2021 · Explore the benefits of 3D-SOC design and backside interconnects for future high-performance systems.
[59]
Chiplets: piecing together the next generation of chips (part I) - IMEC
Jul 16, 2024 · Compared to the microbumps used in 2.5D, hybrid bonding in a 3D stack yields substantially smaller pitches. Is it possible to use hybrid bonding ...Missing: 2021 | Show results with:2021
[60]
Hybrid Bonding Moves Into The Fast Lane
Jul 21, 2022 · Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding dielectric.<|separator|>
[61]
Complementary FET as scaling contender for nodes beyond N3 | imec
Jun 20, 2018 · It offers a potential area scaling of both standard cells (SDC) and memory SRAM cells by 50%. The CFET is a further evolution of the vertically ...
[62]
CFET (complementary FET) - IMEC
Jun 16, 2022 · CFET is an attractive device architecture for beyond 1nm logic. Imec explores two different integration schemes: monolithic and sequential.
[63]
Will CFETs Help The Industry Go Vertical?
Jun 15, 2023 · Imec's Liu expects monolithic CFETs to provide up to 15% more area scaling. Monolithic CFET fabrication is likely to be less expensive in part ...
[64]
GaAs nano-ridge laser diodes fully fabricated in a 300 mm CMOS ...
Jul 28, 2023 · Here, we report the first electrically driven GaAs-based multi-quantum-well laser diodes fully fabricated on 300 mm Si wafers in a CMOS pilot ...
[65]
Ultra-scaled FETs with 2D-material channel - IMEC
Dec 8, 2019 · Imec shows excellent performance in ultra-scaled FETs with 2D-material channel. 2D materials paving the way to extreme scaling for logic and memory transistors.
[66]
Introducing 2D materials in the logic technology roadmap - IMEC
Mar 15, 2021 · Initially, MoS2-based devices were shown to be the most mature, with highest experimental reported mobility values coming close to the ...
[67]
Present and future of micro-transfer printing for heterogeneous ...
Jan 3, 2024 · We present the current state of the art in micro-transfer printing for heterogeneously integrated silicon photonic integrated circuits.
[68]
[PDF] A monolithic III-V on Si integration technology utilizing 300mm ...
The integration of this technology is demonstrated on two different III-V material stacks, GaAs and InP, using standard 300 mm fabrication in a CMOS pilot line, ...
[69]
NanoIC: Europe's pilot line to enable future compute systems - IMEC
Oct 21, 2024 · The NanoIC pilot line, focused on innovation through collaboration of advanced logic, novel memories, and advanced interconnects, aims to fulfill the European ...Missing: empirical | Show results with:empirical
[70]
AI research | imec
Imec's AI research combines deep knowledge of (beyond) CMOS semiconductor technologies with expertise on algorithms and architectures.Missing: 2020-2023 | Show results with:2020-2023
[71]
Neuromorphic hardware | imec
Neuromorphic hardware, like IMEC's spiking neural networks (SNN), mimics biological neurons, reducing power use and latency for sensor fusion.
[72]
Building a low-latency, low-power & accurate SNN chip - IMEC
May 31, 2021 · The chip builds on an entirely event-based digital architecture, and was implemented in low-cost 40nm CMOS technology. It supports event-driven ...
[73]
Imec Builds World's First Spiking Neural Network-Based Chip for ...
Apr 28, 2020 · “This chip meets the industry's demand for extremely low-power neural networks that truly learn from data and enable personalized AI. For its ...<|separator|>
[74]
Optimizing event-based neural networks on digital neuromorphic ...
Mar 28, 2024 · Neuromorphic processors promise low-latency and energy-efficient processing by adopting novel brain-inspired design methodologies.
[75]
Imec and GLOBALFOUNDRIES Announce Breakthrough in AI Chip ...
Jul 8, 2020 · The new chip is optimized to perform deep neural network calculations on in-memory computing hardware in the analog domain.
[76]
AI uses too much energy. How can we solve this problem? - IMEC
Feb 15, 2021 · Recently, imec demonstrated an Analog Inference Accelerator, achieving 2,900 trillion operations per Joule – which is already ten times more ...Missing: benchmarks | Show results with:benchmarks
[77]
AI Chip Lends Credence and Application to Analog in-Memory ...
Relying on an analog circuit, a new AI chip from imec and GlobalFoundries can perform in-memory computations with an energy efficiency 10 to 100 times.
[78]
IMEC proposes 'reconfigurable' AI chips ... - eeNews Europe
May 19, 2025 · A programmable network-on-chip will then be able link and program resources to address algorithm requirements dynamically or at run time. The ...
[79]
Optical interconnects for more I/O bandwidth | imec
Join imec's optical I/O program to build next-gen optical interconnects that combine higher bandwidths with lower costs and energy use.
[80]
New silicon photonics technology delivers faster data traffic - IMEC
May 5, 2017 · Imec has developed a platform for silicon photonics for high-speed optical links for data, telecom and sensing applications.Missing: Malaga | Show results with:Malaga
[81]
[PDF] Silicon Photonics Platform for 50G Optical Interconnects - Cadence
Sep 7, 2017 · The 50G silicon photonics platform includes a 50G NRZ platform, passive devices, optical I/O module, and co-integration of active and passive ...Missing: Malaga | Show results with:Malaga
[82]
Silicon photonics technology for next-generation datacenter ... - IMEC
Dec 3, 2019 · Over the next few years, datacenter operators will upgrade their networks to 400Gb/s optical links – by aggregating 4 100Gb/s lanes per link – ...
[83]
Imec demonstrates progress towards die- and wafer-level optical ...
Jun 3, 2024 · Imec is developing a process flow for direct die-to-wafer hybrid bonding at interconnect pad pitches well below 10 μm, down to 1 μm.
[84]
Beyond-110GHz C-band GeSi EAM - IMEC
Oct 2, 2025 · Achieving a net data rate of 400Gb/s per lane, imec's GeSi EAM heralds a new generation of compact, high-bandwidth, low-latency, ...<|separator|>
[85]
Interfacing silicon photonics for high-density co-packaged optics | imec
Nov 26, 2024 · This article focuses on optical interfacing challenges for high-density co-packaged optics (CPO) applications.Missing: demos | Show results with:demos
[86]
Navigating thermal challenges in advanced systems on chip | imec
Apr 22, 2025 · This article summarizes insights from simulations based on four recent imec papers. The simulations quantify thermal challenges in advanced nodes.
[87]
Neural probes: tracking the activity of individual neurons | imec
These are small brain implants that contain electrodes for recording the electrical signals from neurons.
[88]
Neuropixels 2.0: A miniaturized high-density probe for stable, long ...
The shared movement of the traces across depth reveals relative motion of neurons across the whole probe over both fast (<1 min) and slow (~10 min) timescales.
[89]
Large-scale high-density brain-wide neural recording in nonhuman ...
Jun 23, 2025 · The Neuropixels 1.0 probe has also been used to record neurons in both human and nonhuman primates (NHPs) such as macaques, but its 10-mm length ...
[90]
Ultra-high-density Neuropixels probes improve detection and ...
Sep 30, 2025 · To understand the neural basis of behavior, it is essential to sensitively and accurately measure neural activity at single-neuron and ...
[91]
Closer to understanding the brain - IMEC
Oct 18, 2021 · Neuropixels 2.0 packs over 5000 recording sites on a tiny brain implant enabling neuron recordings across brain regions and circuits. This will boost our ...
[92]
Recording the Brain at Work with Thousands of Sensors
Jun 21, 2021 · The next-generation Neuropixels 2.0 probe can record from more than 5000 sites in the brain, while minimizing tissue damage.
[93]
Advancing neurotech from brain surface to brain depths | imec
Jun 24, 2024 · New research into higher-density neural probes, more extensive electrode coverage of the brain surface, and electrical stimulation ability.
[94]
CMOS MEA for high-throughput, multi-modal cell interfacing | imec
Leveraging the miniaturization and integration power of chip technology, imec's CMOS multi-electrode array is a compact system for cell interfacing.Missing: organoids | Show results with:organoids
[95]
How chip technology will decipher brain diseases - IMEC
Dec 21, 2020 · Imec's chip technology instrumental is decoding brain diseases. By growing relevant circuits on chip, the mechanisms behind Parkinson's can ...
[96]
Merck and imec develop MicroPhysiological Systems platform
May 20, 2025 · This first-of-its-kind co-development and collaboration program intends to integrate cutting edge organoid biology models with advanced ...
[97]
Organ-on-a-chip technology | imec
Organ-on-a-chip technology. By mimicking human physiology on silicon, we improve our biological models without resorting to animal testing.
[98]
Miniaturization of medical devices is crucial for space exploration
Jan 30, 2020 · miDiagnostics is developing a new generation of disposable tests that require only drops of blood and allow detection of cells, proteins ...
[99]
Imec nanotechnology life sciences space
Jan 25, 2021 · To test performance, a drop of blood will pass through the isolated nanofluidic processor during the 20-25 seconds of microgravity in a ...
[100]
miDiagnostics' blood testing device evaluated by imec for use in ...
Nov 19, 2019 · Presently, miDiagnostics has developed a research prototype that can perform a complete cell blood count (CBC) from only drops of blood. In ...
[101]
miDiagnostics to commercializes imec's breath sampler
Oct 14, 2021 · Imec's technology captures exhaled breath aerosols for COVID-19 diagnosis using a unique chip, and is licensed to miDiagnostics for ...Missing: VOC | Show results with:VOC
[102]
Breath sampler | imec
Based on standard chip technology, this testing tool promises to be an easy way to accurately determine disease biomarkers in breath.
[103]
Molecular detection of SARS-COV-2 in exhaled breath at the point ...
Aug 30, 2022 · Performed clinical studies demonstrate that the sensitivity and specificity of exhaled breath-based testing for SARS-CoV-2 is comparable to that ...
[104]
[PDF] Museic V2 | IMEC
• Supports ECG, EEG, EMG, BIO-Z, and GSR. • Compact readout with state-of-the-art performance. • Photo-plethysmograph (PPG) readout. • Sensitivity: <10 nA ...
[105]
Flexible ECG Patch Extended To Enable Arrhythmia Detection
Jul 14, 2008 · IMEC's ECG patch achieves a 99.93% sensitivity and a 98.28% positive predictivity for QRS detection on 86994 beats. For delineation over ...Missing: GSR | Show results with:GSR
[106]
Comfortable, disposable health patch | imec
Jan 8, 2019 · It also includes an accelerometer for tracking physical activity, an ECG heart activity tracker and bioelectrical impedance monitoring.Missing: GSR | Show results with:GSR
[107]
Technology for vital sign monitoring devices - IMEC
Wearable devices monitor a variety of vital signs. Wearable prototypes such as a disposable health patch contain a biomedical sensor system-on-chip that can ...Missing: flexible | Show results with:flexible
[108]
Solid-state nanopores for biosensing and sequencing - IMEC
Roswell Biotechnologies and Imec to Develop First Molecular Electronics Biosensor Chips for Infectious Disease Surveillance, Precision Medicine and DNA Storage.Unleash Full Potential Of... · Value Of Solid-State... · Integration With Cmos
[109]
Solid-state nanopores for single-molecule sensing - IMEC
Oct 22, 2024 · Sequencing via nanopores has the advantage of tackling long reads which translates into more reliable and faster results. For proteomics, ...
[110]
Massive single-molecule sensing arrays for proteomics - IMEC
Oct 23, 2024 · Moreover, imec has the established capability to produce master templates using its 300mm pilot line, with very small and high-density features.<|separator|>
[111]
Imec ITF World 2025: Gut Health, BioSensing and Lead-Free SWIR ...
May 20, 2025 · One of the demonstrations at imec today was a highly miniaturized ingestible sensor prototype, developed at OnePlanet Research Center, claiming ...
[112]
OnePlanet presents prototype of ingestible sensor to monitor gut ...
May 19, 2025 · The ingestible sensor measures redox balance, pH levels, and temperature, and is smaller than current endoscopes, measuring every 20 seconds.
[113]
Microfluidics | imec
Microfluidics allows precise control of fluids on a small scale, enabling compact devices like 'labs on chips' for various lab functions.White Paper: Monolithic... · Active Microfluidics · Integrated Fluidics System
[114]
PCR on a microfluidic chip: accelerated tests on silicon | imec
PCR on a microfluidic chip offers faster, more accurate, and affordable results, with accelerated amplification, cost reduction, and increased accuracy.
[115]
Imec collaborates with Janssen to advance precision medicine to ...
Feb 6, 2020 · ... biosensing devices that can scan blood or other fluids for diseases, all in only a fraction of the time that is needed with today's instruments.
[116]
Biosensor technology - IMEC
Imec combines its CMOS platform with on-chip microfluidics and electrical/photonic sensors. This enables chips for fast and accurate detection of cells, DNA, ...Miniaturizing Biosensors... · Other Technology Platforms · High-Throughput Cytometry...Missing: precision | Show results with:precision
[117]
Tandem Solar Cell - TaiyangNews
24.16% Efficiency Claim for CIGS-Perovskite Tandem Cell. Apr 17, 2020. 27.1% Perovskite/Si Tandem Cell from IMEC · Technology · 27.1% Perovskite/Si Tandem Cell ...
[118]
Imec - Company Profile and News - Perovskite-Info
Jun 6, 2024 · Imec leverages its state-of-the-art R&D infrastructure and its team of more than 5,500 employees and researchers for advanced semiconductor R&D ...
[119]
Imec presents inverted perovskite solar cell with 24.3% efficiency
Imec presents inverted perovskite solar cell with 24.3% efficiency. The researchers of the Belgian research institute used a dual-layer ...
[120]
More scalable and efficient thin-film tandem solar cells - IMEC
Oct 15, 2024 · Imec demonstrated perovskite-on-CIGS tandem cells with efficiencies near 30% for small cells and 21% for larger modules, bringing these ...
[121]
Imec and Partners Demonstrate Long-Term Outdoor Stability of ...
Jan 7, 2025 · The solar modules were tested under real-world conditions for two years, achieving a 78% power efficiency retention after the first year.
[122]
Enhancing efficiency and stability of Perovskite solar cells - IMEC
Jul 25, 2023 · In this article, dr. Tom Aernouts presents an ammonium salt treatment to enhance two critical interfaces, creating highly efficient, stable, and scalable ...Missing: humidity MTTF
[123]
Solid-state micro-batteries and formable batteries - IMEC
These are batteries that use solid electrolytes instead of the liquid or gel electrolytes found in traditional lithium-ion batteries. Advantages are: improved ...
[124]
Lithium-metal achieves 1070 Wh/L - IMEC
Sep 19, 2024 · It boasts an impressive energy density of 1070 Wh/L, compared to 800 Wh/L for state-of-the art lithium-ion batteries.Missing: 2022 | Show results with:2022
[125]
Imec spin-off SOLiTHOR closes a €10M seed investment round to ...
May 16, 2022 · Imec spin-off SOLiTHOR closes a €10M seed investment round to develop a new disruptive solid-state battery cell technology · About SOLiTHOR.
[126]
Boosting GaN performance | imec
May 7, 2019 · Imec paves the way to boosting GaN performance and enabling true GaN-IC technology. Imec demonstrates fully monolithical co-integration of GaN half-bridge with ...<|separator|>
[127]
Imaging technology development based on CMOS | imec
Imec's specialty image sensors are based on CMOS image technology and tuned to meet exceptional specifications such as extreme speeds or ultra-low noise.
[128]
Imec integrates thin-film pinned photodiode into superior short-wave ...
Aug 14, 2023 · “The prototype 4T image sensor showed a remarkable low read-out noise of 6.1e-, compared to >100e- for the conventional 3T sensor, demonstrating ...
[129]
ON Semi on a Roll With Image Sensors - EE Times
Apr 17, 2014 · Cypress's image sensor technology was rooted in IMEC spinoff FillFactory in Belgium, which Cypress bought in 2004. ... Armed with very fast global ...
[130]
Cmosis broadens CMOS portfolio - Optics.org
An ability to capture high-resolution in 4K HD format, with high dynamic range and global shutter, make the sensor suitable for broadcasting, traffic monitoring ...
[131]
https://www.imec-int.com/en/imec-magazine/imec-magazine-october-2017/image-sensor-combining-the-best-of-different-worlds
[132]
Image sensor combining the best of different worlds - IMEC
Sep 26, 2017 · Imec has been developing a new solution that combines CCD pixels and CMOS readout in one technology, enabling a single imager chip with both CCD and CMOS ...
[133]
ADAS technology | imec
Next-generation ADAS technology. Take advantage of imec's IoT expertise to develop car sensor technologies that will severely mitigate human driving errors.
[134]
Imec lowers infrared cost with monolithic quantum dot IR sensor
The Acuros SWIR camera has HD resolution of 1,920 x 1,080 pixels (2.1 megapixels). It uses a 400nm to 1,700nm broadband image sensor with colloidal quantum dot ...<|separator|>
[135]
SWIR Sensor Developed in Research Project Uses Lead-free ...
Researchers developed a proof-of-concept lead-free QD photodiode integrated onto a shortwave infrared optical sensor through the Q-COMIRSE project. Courtesy of ...
[136]
Imec reports monolithic thin-film image sensor for the SWIR range ...
Oct 21, 2019 · Test photodiodes on silicon substrate achieve an external quantum efficiency above 60 percent at 940nm wavelength, exceeding the state-of ...Missing: floor | Show results with:floor
[137]
imec hyperspectral: Hyperspectral imaging from visible to SWIR
Machine vision. Use imec's real-time hyperspectral sensor technology to guide robots, keep an eye on production lines, and automate unpredictable processes.Missing: global shutter<|separator|>
[138]
First SWIR sensor with non-lead quantum dots ... - eeNews Europe
Dec 16, 2024 · The Q-COMIRSE project in Belgium has shown a prototype shortwave infrared (SWIR) sensor with indium arsenide (InAs) rather than lead for the ...
[139]
SWIR cost cut: Imec achieves 1.82µm pixels
Imec presented a shortwave infrared quantum dot image sensor with a pixel pitch of 1.82μm at the IEEE International Electron Devices Meeting (IEDM).
[140]
imec integrates thin-film pinned photodiode in SWIR sensors
Aug 20, 2023 · As a result, infrared images can be captured with less noise, distortion or interference, and more accuracy and detail.” Pawel Malinowski, ...
[141]
Imec Taps Pinned Photodiode to Build a Better SWIR Sensor
Oct 25, 2023 · With the new elements strategically placed within the traditional PDD structure, the prototype 4T image sensor showed a low readout noise of 6.1 ...
[142]
GaN power devices | imec
Imec studies how to make GaN devices more reliable and performant by diving deep into device physics, power switching and failure mechanisms. Next to this, imec ...
[143]
GaN takes on SiC with imec breakthrough ...
Apr 29, 2021 · Imec demonstrate 1200V GaN process on 200mm silicon wafers for the first time to take on SiC with lower cost power devices.
[144]
Webinar: Power Electronics (GaN & SiC) - YouTube
Mar 23, 2023 · Urmimala Chatterjee (imec) and Tobias Erlbacher (Fraunhofer IISB) will present a webinar on Power Electronics. Urmimala and Tobias work on ...
[145]
Imec launches 300mm GaN program to develop advanced power ...
Oct 6, 2025 · Imec announces the launch of a new program track centered around 300mm GaN technology development for low and high voltage power electronics ...
[146]
140 GHz radar: smarter, safer cars within everyone's reach - IMEC
Dec 17, 2024 · 140 GHz radar offers high-resolution sensing at a lower cost compared to lidar, making it a promising addition to automotive sensor suites.
[147]
Radar and lidar technology | imec
IMEC designs high-resolution, compact radar solutions, including 79GHz, 140GHz, and 8 GHz radars, and custom-made on-chip lidar.Missing: vehicles | Show results with:vehicles
[148]
Imec delivers distributed radar breakthrough for ADAS - EDN Network
Apr 29, 2025 · At OFC 2025, imec unveiled a proof of concept for a photonics-based CDM FMCW 144-GHz distributed radar system, which could improve ADAS.
[149]
Novel architectures for machine learning and artificial intelligence
lower latency – instant reactions become possible in settings such as autonomous driving; increased privacy and security – our personal data are no longer ...
[150]
SENSAI: digital twin for next-gen automotive sensors - IMEC
SENSAI uses digital twin technology to model next-gen automotive sensors, using AI to expand data and predict performance improvements.
[151]
https://www.imecitf.com/world/2024
[152]
ITF World 2024
Join us to explore semiconductor advances and deep-tech solutions for health, pharma, automotive, AI, and other application domains.<|separator|>
[153]
City of Things - IMEC
The City of Things program laid the groundwork for a region in which technology can fully contribute to a more enjoyable and sustainable life for everyone.
[154]
imec, Antwerp and Flanders Establish Smart City Living Lab
Jan 6, 2017 · In the Smart City Living Lab, businesses, researchers, local residents and the city itself will experiment with smart technologies.<|separator|>
[155]
imec.icon project - BLUESS
The BLUESS project will develop an autonomous, energy-efficient BLEv5 mesh network for smart lighting capable of supporting numerous third-party devices.
[156]
[PDF] An Open Smart City Vision and Architecture - imec Vlaanderen
Oct 23, 2019 · It supports geo- and temporal queries which are mandatory for effectively using the smart city IoT data. Figure 7 illustrates how adding ...
[157]
Vision: A living lab for smart cities worldwide - IMEC
Jan 1, 2017 · The 60 GHz solution for backhaul networks will be developed to expand the available communication bandwidth quickly and seamlessly when major ...
[158]
Imec and GLOBALFOUNDRIES Announce Breakthrough in AI Chip ...
Jul 8, 2020 · Imec and GLOBALFOUNDRIES Announce Breakthrough in AI Chip, Bringing Deep Neural Network Calculations to IoT Edge Devices.
[159]
Imec and TNO launch Digital Twin of the city of Antwerp
Sep 27, 2018 · The real-time data of the digital twin are indispensable for this. For Flemish cities, it is a step towards becoming true Smart Cities.” “ ...Missing: backhaul | Show results with:backhaul
[160]
Surv-AI-llance - IMEC
The solution offers significant efficiency and accuracy improvements and runs using edge intelligence, which enables distributed devices to process and analyze ...
[161]
The IoT is coming… but can it be made secure? - IMEC
Jun 5, 2017 · Researchers from imec – COSIC – KU Leuven developed an innovative cryptography chip that can protect low-power sensors and even RFID tags.
[162]
imec.icon project - CORRELATE
The CORRELATE project seeks to revolutionize IoT systems for a more sustainable and efficient future, optimizing energy consumption through selective device ...
[163]
IMEC forms 'more-than-CMOS' alliance with TSMC - EE Times
“We will develop CMORE platforms for specific applications and have a partnership with for TSMC to take on the processes from there,” van den Hove told ...
[164]
Vertical Compute, a new imec spin-off, raises €20 million - News
Jan 14, 2025 · Vertical Compute, a new imec spin-off, raises €20 million ... New deep-tech semiconductor startup tackling AI's compute memory bottleneck.Missing: examples | Show results with:examples
[165]
Axithra, A Spin-off of imec and Ghent University, Raises 10M Euro
Sep 6, 2023 · Axithra, a new spin-off of imec and Ghent University, today announced a 10 million euro seed round, securing the first two years of R&D.<|separator|>
[166]
Introducing IMEC, the pioneering research and innovation hub in ...
Jul 2, 2020 · Introducing IMEC, the pioneering research and innovation hub in nanoelectronics and digital tech based in Europe. 02 July 2020. Ground ...Missing: scope | Show results with:scope
[167]
Crucial role for imec in EU Chips Act
May 21, 2024 · This pilot line taps into the EU Chips Act vision to accelerate innovation, drive economic growth, and strengthen Europe's semiconductor ecosystem.Missing: sovereignty | Show results with:sovereignty
[168]
ASML and imec open joint High NA EUV Lithography Lab offering ...
Jun 3, 2024 · For imec and its partners, the High NA EUV Lithography Lab will act as a virtual extension of our 300 mm cleanroom in Leuven, enabling us to ...
[169]
Luc Van den hove (imec): "We live on our reputation. It's the essence ...
Jul 17, 2025 · Van den hove has the numbers: every euro invested returns four in taxes, economic impact is eleven times the investment. But frames matter ...
[170]
European labs led by imec to receive $2.7 billion in Chips Act funding
May 21, 2024 · Leading European research labs will receive 2.5 billion euros ($2.72 billion) in funding under the European Chips Act to set up a pilot line ...<|separator|>
[171]
Logic technology scaling options for 2nm and beyond - IMEC
Jun 14, 2021 · Scaling options include GAA, forksheet, and CFET architectures, with 2D materials like WS2, and a move to 1nm CFET family.
[172]
Challenges of Wafer‐Scale Integration of 2D Semiconductors for ...
Sep 7, 2022 · Further scaling of Si-based devices below 10 nm gate length is becoming challenging due to reduced channel control. ... At these gatelengths sub 5 ...
[173]
IMEC's Advanced Node Yield Model Now Addresses EUV Stochastics
Aug 23, 2025 · The Stochastics Resolution Gap limits the manufacturability of EUV lithography, which can theoretically achieve resolution limits near 10 nm. As ...Missing: mitigation | Show results with:mitigation
[174]
Siemens-imec collaboration reduces stochastic failures in EUV ...
Sep 11, 2025 · Siemens stochastic-aware OPC reduces EUV stochastic failures at wafer level for SRAM and logic, validating predictive modeling with ...
[175]
Sailing along the stochastic cliffs - IMEC
Jun 28, 2019 · Stochastic printing failures are random, non-repeating, isolated defects such as microbridges, locally broken lines and missing or merging contacts.Missing: variability | Show results with:variability
[176]
Novel Assembly Approaches For 3D Device Stacks
Jun 30, 2025 · Imec previously showed that implementing backside power imposes a 10% to 30% thermal penalty (ECTC 2024). This year, Oprins' group simulated the ...
[177]
TCAD Simulation Challenges For Gate-All-Around Transistors
Dec 17, 2024 · One of the challenges is handling the thin Si layers that come with GAA technology, where Si channel thickness scales down to ~4nm, as opposed ...
[178]
IMEC revenue (M€) and ratio of Flemish government subsidies...
Flemish government subsidies have now fallen to 15% of IMEC's revenue (see Figure 1). 7 11 The five remaining directors were selected by F lemis h industry (two ...Missing: budget EU
[179]
FAQ about Intellectual Property Rights (IPR) - IMEC
Browse our list of frequently asked questions about IPR in imec.icon projects: Background, Foreground and Sideground knowledge, ownership, use of open source, ...<|control11|><|separator|>