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Self-aligned gate

A self-aligned gate is a fabrication technique in metal–oxide–semiconductor field-effect transistor (MOSFET) technology that uses the gate electrode itself as a mask to define the adjacent source and drain regions, ensuring precise alignment without requiring additional lithographic steps and thereby reducing parasitic overlap capacitances between the gate and source/drain.^[1] This method, pivotal to modern integrated circuit (IC) design, was conceived by Robert W. Bower in 1965 while at Hughes Research Laboratories and patented in 1969 as U.S. Patent No. 3,472,712, enabling the creation of faster, more reliable, and denser transistors essential for semiconductor advancement.^[2]^[3] The self-aligned gate approach addressed critical limitations of earlier metal-gate MOSFETs, which relied on aluminum electrodes that melted at approximately 660°C, preventing the high-temperature diffusion or ion implantation processes (around 1000°C) needed to form source and drain regions after gate deposition.^[4] By shifting to polycrystalline silicon (polysilicon) gates—doped to conduct electricity and stable up to 1414°C—the technology allowed the gate to be patterned first, followed by self-aligned doping of the source and drain using the gate as a natural barrier, which minimized lateral diffusion and overlap by as much as 0.5–1 micrometer compared to non-aligned processes.^[5] This innovation, independently pursued by teams like Kerwin, Klein, and Sarace at Fairchild Semiconductor in 1969, dramatically improved device performance: transistor speeds increased by 3–5 times at the same power consumption, or power usage dropped by a similar factor at equivalent speeds, while circuit density doubled and leakage currents reduced by up to 100 times.^[4]^[5] Federico Faggin further refined the technique at Fairchild in 1968, integrating it with silicon-gate technology to produce the first commercial self-aligned gate IC, the 3708 8-bit analog multiplexer, and later applying it at Intel for the groundbreaking 4004 microprocessor in 1971, which marked the dawn of the microprocessor era and non-volatile memories.^[5] Beyond speed and density gains, self-aligned gates enhanced reliability through compatible high-temperature processing with materials like phosphosilicate glass (PSG) for passivation, lowering PMOS threshold voltages by about 1.1 V (a 30% improvement) and enabling buried contacts and bootstrap circuits for more complex dynamic logic.^[4] Today, variations such as self-aligned silicide (salicide) extend this principle to further reduce contact resistances in advanced nodes, underscoring its enduring role as the foundation for all contemporary CMOS-based electronics, from smartphones to high-performance computing.^[3]

Introduction

Definition and Core Principles

The self-aligned gate is a pivotal fabrication technique in metal-oxide-semiconductor (MOS) transistor production, where the gate electrode itself serves as a mask to define the precise boundaries of the source and drain regions, thereby eliminating the need for separate manual alignment steps that were prone to errors in earlier processes.^[6] This approach ensures that the source and drain junctions are formed directly adjacent to the gate edges without unintended offsets, enabling tighter scaling and higher device density in integrated circuits.^[7] First practically implemented for integrated circuits in 1968 by Federico Faggin at Fairchild Semiconductor, building on earlier concepts such as Robert W. Bower's 1965 proposal, it marked a foundational shift toward modern MOS technology.^[7]^[8] At its core, the technique leverages the gate structure to control dopant implantation or diffusion, positioning the heavily doped source and drain regions such that they abut the gate dielectric without overlap, which fundamentally reduces parasitic effects.^[6] In a basic MOS transistor with self-aligned features, the structure consists of a p-type silicon substrate (for n-channel devices), a thin gate oxide layer, a polysilicon gate electrode spanning the channel region, and n+ source/drain diffusions precisely aligned to the gate edges, forming the conductive path modulated by gate voltage.^[7] This alignment minimizes the gate-to-source and gate-to-drain overlap, directly lowering the associated parasitic capacitance that can degrade switching speed and power efficiency. The reduction in overlap capacitance arises from the precise positioning, where the overlap area A is minimized to near zero compared to misaligned predecessors.^[6] The overlap capacitance is given by the formula

C_{ov} = \frac{\epsilon \cdot A}{t_{ox}}

where \epsilon is the permittivity of the gate oxide, A is the overlap area between the gate and source/drain, and t_{ox} is the oxide thickness; self-alignment effectively shrinks A, yielding capacitances 3–5 times lower than in non-self-aligned designs and thereby enhancing transistor performance.^[9]^[6] A key enabling principle is the use of polycrystalline silicon (polysilicon) or similar refractory conductive materials for the gate electrode, which can endure the high-temperature annealing steps required for source/drain doping after gate patterning—unlike aluminum gates in prior methods that would melt or diffuse uncontrollably.^[7] This material choice allows the gate to be fabricated early in the process, acting as a robust mask during subsequent ion implantation, while also serving as an interconnect layer to further optimize circuit layout.^[6]

Role in MOS Transistor Evolution

The introduction of self-aligned gates marked a pivotal evolutionary shift in MOS transistor design, transitioning from metal-gate structures to silicon-gate transistors during the late 1960s and early 1970s. This change replaced aluminum gates with polycrystalline silicon, allowing for precise self-alignment of the gate with source and drain regions through diffusion processes that used the gate itself as a mask. As a result, MOS integrated circuits achieved significantly higher packing densities, with silicon-gate designs occupying roughly half the chip area of their metal-gate predecessors while delivering 3-5 times faster switching speeds.^[7]^[5] This advancement profoundly impacted computing power by enabling the fabrication of more complex microprocessors, exemplified by the Intel 4004 released in 1971, which integrated 2,300 transistors on a single chip using self-aligned silicon-gate technology. The reduced power dissipation and enhanced reliability of these transistors—stemming from lower threshold voltages and minimized leakage currents—facilitated the design of dense, efficient circuits that were unattainable with metal-gate approaches. By supporting such high levels of integration, self-aligned gates heralded the onset of the Very Large Scale Integration (VLSI) era, shifting the semiconductor industry toward MOS dominance over bipolar technologies for most applications by the mid-1970s.^[5]^[7] Self-aligned gates played a prerequisite role in MOS transistor scaling, permitting the pursuit of sub-micron feature sizes by substantially reducing parasitic capacitances between the gate and source/drain regions, which had previously limited performance and density. This precision alignment minimized overlap areas that contributed to unwanted charge storage and signal delays, directly bolstering the exponential growth in transistor density central to Moore's Law. Without these improvements, achieving the consistent channel control necessary for advanced scaling would have been infeasible, as self-aligned structures ensured gates were positioned accurately over channels during fabrication.^[10]^[5] Quantitatively, the technology reduced channel length variation from approximately 1-2 μm due to mask misalignment tolerances in older metal-gate methods—where separate masks for gates and diffusions often led to overlaps or shorts—to near-zero variation, thereby enhancing manufacturing yield and transistor speed. This alignment accuracy allowed for tighter control over effective channel lengths, mitigating short-channel effects and enabling reliable operation at smaller scales that propelled integrated circuit evolution.^[11]^[12]

Historical Development

Early Innovations at Fairchild Semiconductor

The self-aligned gate concept originated earlier with Robert W. Bower's 1965 proposal at Hughes Research Laboratories, patented in 1969 (U.S. Patent No. 3,472,712), and was independently developed in 1967 by Robert Kerwin, Donald Klein, and John Sarace at Bell Labs, who patented it in 1969 (U.S. Patent No. 3,475,234).^[2]^[13]^[8] In 1968, Federico Faggin, while working at Fairchild Semiconductor's R&D laboratory, invented the self-aligned silicon gate process, a pivotal advancement that enabled precise alignment of the gate electrode with source and drain regions in MOS transistors without relying on separate masking steps.^[7] This innovation built upon earlier concepts but was the first to achieve commercial viability through practical fabrication techniques. Faggin's work addressed key limitations in metal-gate MOS processes, such as misalignment and high resistance, by substituting polycrystalline silicon for aluminum gates.^[14] A critical experiment in this development involved the use of phosphorus-doped polysilicon gates, which allowed source and drain dopants to be diffused at high temperatures—up to 1000°C—without causing gate degradation or dopant redistribution that could lead to short channels.^[14] The heavy doping with phosphorus rendered the polysilicon conductive and thermally stable, permitting the gate structure to serve as an effective mask during subsequent diffusion steps, thereby achieving sub-micron alignment tolerances essential for denser integration.^[5] By April 1968, Faggin had fabricated the first functional MOS transistors using this full self-aligned process, demonstrating enhanced speed and reliability.^[7] Supporting this breakthrough was foundational work by Robert N. Noyce and colleagues at Fairchild on silicon-gate MOS technology, including Noyce's 1965 internal memo outlining a polycrystalline, self-aligned silicon-gate approach for large-scale integration.^[15] Their efforts culminated in the first demonstration of self-aligned n-channel devices, validating the process for high-performance applications. This collective innovation at Fairchild marked a turning point in MOS evolution, enabling the transition from discrete components to complex integrated circuits.^[14] The inventions were protected through patents, notably U.S. Patent 3,673,471 (1972) by Thomas Klein and Federico Faggin, which detailed the use of doped polysilicon gates for self-alignment via the gate acting as a diffusion mask.^[5] An earlier related patent, U.S. 3,472,712 (1969) by Robert W. Bower, had proposed insulated gate concepts, but Faggin's implementation at Fairchild integrated these into a manufacturable process.^[16]

Commercialization and Impact at Intel

Federico Faggin, having pioneered the self-aligned silicon-gate technology at Fairchild Semiconductor, joined Intel in April 1970 and adapted it for the company's MOS integrated circuits, significantly advancing production efficiency and device performance.^[17] This transition built on Intel's early adoption of the process for its 1101 MOS memory chip in 1969, but Faggin's enhancements, including buried contacts, enabled more complex logic designs.^[7] The technology's commercial debut came with the Intel 4004 microprocessor in 1971, the first single-chip CPU, which integrated 2,300 transistors using a 10 μm process to achieve unprecedented density and speed for programmable logic.^[18] Faggin led its design, leveraging self-aligned gates to fit the CPU functions onto a compact die, marking a pivotal shift from custom bipolar circuits to general-purpose MOS processors.^[19] Building on this foundation, the self-aligned gate process powered the Intel 8008 in 1972, an 8-bit evolution of the 4004, and the more powerful 8080 in 1974, which further reduced manufacturing costs by up to 40% through improved yields and smaller feature scaling while boosting transistor integration density.^[17] These advancements lowered the price of computing components, enabling broader applications in calculators, terminals, and early computers.^[20] Intel's implementation spurred industry-wide adoption, with the company licensing microprocessor designs and the underlying self-aligned gate process diffusing to competitors, resulting in its standard use for DRAM and logic chips across the sector by the mid-1970s.^[7] This proliferation accelerated the transition to high-density MOS fabrication, reducing costs and driving exponential growth in semiconductor integration.^[17]

Technical Foundations

Comparison with Pre-Self-Aligned Methods

In the conventional aluminum-gate MOSFET process prevalent in the early days of integrated circuit fabrication, separate photolithographic masking steps were required for defining the source and drain regions, followed by the gate electrode. This sequential approach, involving diffusion or implantation for source/drain doping prior to gate patterning, inherently introduced misalignment tolerances of approximately 1-2 μm between the gate and the source/drain edges due to limitations in mask alignment precision during that era.^[11]^[4] Such misalignment resulted in unintended gate overlap with the heavily doped source and drain regions, significantly increasing parasitic overlap capacitance (C_{ov}), which could constitute up to 2.5 times the intrinsic gate capacitance in perfectly aligned cases and even higher in misaligned scenarios, thereby degrading switching speeds through enhanced Miller effect coupling.^[11] Additionally, the thermal budget was severely constrained by aluminum's low melting point of 660°C, preventing high-temperature post-gate annealing or diffusion steps necessary for optimal junction formation and gettering, which in turn necessitated larger device dimensions to accommodate diffusion spreads and reduced manufacturing yields.^[4]^[5] By the 1970s, as integrated circuit feature sizes shrank toward 5-10 μm to meet demands for higher density, these misalignment-induced variations emerged as a dominant yield limiter, prompting the development of self-aligned gate techniques to mitigate these inefficiencies.^[5]

Mechanisms of Self-Alignment

The self-aligned gate process in MOSFET fabrication relies on the polysilicon gate structure serving as a hard mask to prevent dopant implantation or diffusion into the channel region. The polysilicon gate, typically topped with an overlying oxide or nitride layer for enhanced etch selectivity and protection, blocks high-energy ions or diffusing species from reaching the underlying silicon substrate beneath the gate, thereby defining the channel length precisely without additional masking steps. This masking action ensures that dopants are introduced only in the source and drain areas adjacent to the gate edges, maintaining electrical isolation of the channel.^[21] Lateral diffusion of dopants is controlled such that penetration occurs primarily near the gate edges, forming self-aligned extensions. For n-channel devices, dopants like phosphorus are implanted or diffused into the substrate, but their sideways spread under the gate is minimized by the hard mask, resulting in abrupt junctions.^[22] Alignment precision in self-aligned gates reaches sub-micrometer levels, often below 0.1 μm, limited primarily by the lateral diffusion length during dopant activation anneals. The diffusion length L_d is given by L_d = \sqrt{D \cdot t}, where D is the dopant diffusivity (dependent on species and temperature) and t is the anneal time; for phosphorus at typical anneal conditions (e.g., 900-1100°C), this constrains under-gate encroachment to tens of nanometers, enabling reliable short-channel MOSFETs compared to earlier misaligned metal-gate processes that suffered from larger overlaps.

Manufacturing Process

Primary Fabrication Steps

The fabrication of a self-aligned gate MOS transistor involves a sequence of precise steps starting from substrate preparation and culminating in metallization.^[4] The process begins with a p-type silicon wafer substrate. A thick field oxide layer, approximately 1 μm thick, is grown via thermal oxidation and patterned using photolithography and etching to create isolation structures, such as LOCOS oxide, that electrically separate devices on the wafer and define the active areas for transistors.^[23] A thin gate oxide layer is then grown via thermal oxidation in the active areas to serve as the gate dielectric.^[4] A layer of polysilicon is deposited over the oxide using chemical vapor deposition and heavily doped to create the conductive gate material, forming the initial gate stack.^[4] Photolithography is applied to define the gate pattern, followed by etching to remove excess polysilicon and oxide, leaving the shaped gate electrode in place.^[1]^[4] Source and drain regions are subsequently formed through ion implantation or diffusion of dopants into the substrate, with the polysilicon gate acting as a natural mask to achieve self-alignment; this ensures the regions are precisely positioned adjacent to the gate without additional masking steps. An anneal at high temperature, typically around 1000 °C, follows to activate the implanted dopants and repair lattice damage.^[1]^[4] An insulating layer, such as phosphosilicate glass (PSG), is then deposited over the structure. Contact etching opens windows in this layer to access the source, drain, and gate.^[4] Final processing includes silicide formation on these contacts to lower resistance, followed by metallization with aluminum or similar conductors for interconnections.^[4] Critical alignment during the source/drain formation step is essential for yield, as process variations here contributed to a notable fraction of defects in early implementations.^[4]

Materials and Doping Techniques

In self-aligned gate MOSFETs, the gate electrode is typically constructed from doped polysilicon, which is heavily doped to n+ or p+ conductivity levels using phosphorus oxychloride (POCl3) diffusion for n-type gates. This material selection provides thermal stability during high-temperature processing steps, enduring temperatures up to approximately 1000°C required for dopant activation and annealing without significant degradation. Additionally, polysilicon's compatibility with the underlying silicon oxide dielectric ensures reliable interface properties and prevents reactions that could compromise device integrity.^[24]^[25] The gate dielectric in these structures is formed by thermal oxidation of silicon to produce a silicon dioxide (SiO2) layer, typically 50-100 nm thick, which serves as an effective insulator between the gate and channel. This thermal SiO2 exhibits a breakdown electric field strength of around 10 MV/cm, enabling reliable operation under applied voltages while maintaining low leakage currents. The thickness range balances capacitive coupling with sufficient isolation for early device generations.^[26] Doping techniques for self-aligned gates emphasize precision to achieve shallow junctions and avoid misalignment. For source and drain regions, ion implantation is employed, such as arsenic ions (As+) accelerated at energies of 50-100 keV, to create shallow n-type junctions with controlled depth and minimal lateral spread under the gate. In contrast, the polysilicon gate itself is doped via diffusion processes, like POCl3 for n+ doping, to prevent lattice damage from implantation while ensuring uniform conductivity across the gate structure. This combination allows self-alignment by using the gate as a mask for subsequent source/drain doping.^[27] Early explorations of gate materials included transitions from aluminum, which suffered from electromigration and poor thermal stability, to refractory metals such as tungsten in hybrid configurations for improved conductivity and heat resistance. However, doped polysilicon emerged as the dominant choice due to its seamless integration with silicon processing and enabling of true self-alignment without additional masking steps.^[28]^[29]^[30]

Advantages and Challenges

Key Performance Improvements

The self-aligned gate structure significantly minimizes parasitic overlap capacitance C_{ov} between the gate electrode and the source/drain regions, a substantial improvement over the larger overlaps in non-self-aligned metal-gate processes.^[5] This reduction primarily affects the gate-to-drain capacitance C_{gd}, which degrades circuit speed via the Miller effect. By lowering C_{ov}, the cutoff frequency f_T = \frac{g_m}{2\pi (C_{gs} + C_{gd})} increases, where g_m denotes transconductance, enabling higher-frequency operation in MOS integrated circuits.^[31] Switching delay in 1970s self-aligned gate devices was reduced by a factor of 3–5 compared to prior metal-gate MOSFETs, primarily due to decreased parasitic capacitances and improved gate control.^[32] This enhancement facilitated more complex logic and memory circuits.^[7] Power efficiency improved through lower leakage currents enabled by precise source/drain junction alignment, bringing the subthreshold swing closer to the theoretical ideal of 60 mV/decade and reducing off-state power dissipation.^[4] Overall, self-aligned gates achieved 3-5 times lower power consumption at equivalent speeds relative to non-aligned predecessors.^[32] The technology supported aggressive scaling, enabling channel lengths to shrink to 5 μm by 1975 while maintaining reliable performance, which boosted transistor density and increased chip-scale integration by orders of magnitude—from hundreds of transistors in 1960s MOS ICs to thousands in 1970s designs.^[7]

Limitations and Scaling Issues

As self-aligned gate technology enabled channel lengths to shrink below 1 μm in the late 1980s and early 1990s, short-channel effects emerged as a primary limitation, particularly drain-induced barrier lowering (DIBL), which causes a reduction in threshold voltage and increased off-state leakage.^[33] DIBL arises from the drain electric field penetrating the channel, lowering the potential barrier between source and channel. For effective lengths around 0.25–0.5 μm, DIBL becomes significant, necessitating higher substrate doping levels (up to $10^{17} cm^{-3}) to maintain control, though this increased junction capacitance and body effect. Hot carrier injection further constrained scaling, as high electric fields near the drain junction accelerated carriers to energies sufficient for injection into the gate oxide, degrading transconductance and threshold voltage over time.^[34] In self-aligned structures without mitigation, peak fields reached 5–7 MV/cm for 1 μm channels at 5 V drain bias, leading to gate current densities exceeding 10^{-15} times the drain current after prolonged operation. This reliability issue prompted the adoption of lightly doped drain (LDD) extensions, which reduced field peaking by 60–70% but introduced series resistance trade-offs.^[35] Thermal budget trade-offs posed additional challenges during fabrication, as high-temperature anneals (typically 900–1100°C) required for dopant activation in source/drain regions caused significant redistribution and diffusion, blurring p-n junctions and increasing overlap capacitances.^[36] In self-aligned processes, excessive thermal exposure diffused implanted dopants beyond the intended 0.1–0.2 μm junction depths, exacerbating short-channel effects.^[37] Balancing activation efficiency with minimal diffusion often limited anneal times to seconds via rapid thermal processing, yet residual blurring persisted for sub-0.5 μm gates.^[36] Yield scaling was hindered by lithography limitations, with alignment precision constrained to approximately 0.1–0.15 μm in the early 1990s due to optical stepper resolutions, leading to gate-to-source/drain misalignment variations that increased defect densities.^[38] For 0.5–1 μm technologies, overlay errors of 0.1–0.15 μm resulted in yield drops below 80% for high-density circuits, as even minor shifts amplified junction leakage and short-channel non-uniformities across wafers. Process tweaks, such as enhanced spacers or etch selectivity, were needed to tolerate these tolerances, but fundamental lithographic constraints capped practical scaling without advanced exposure tools.^[38]

Modern Extensions

Adaptations in Advanced Semiconductor Nodes

As semiconductor scaling progressed to sub-100 nm nodes, self-aligned gate processes underwent significant adaptations to address challenges like poly depletion and lithography limitations while preserving precise alignment. In the 45 nm node, polysilicon gates were replaced with metal gates, such as titanium nitride (TiN), to eliminate poly depletion effects that degrade gate capacitance and increase equivalent oxide thickness. This shift was implemented via a replacement metal gate (RMG) process, where a temporary dummy polysilicon gate is patterned and used to define source/drain regions, followed by its selective removal and substitution with the metal gate stack, thereby maintaining the self-alignment of source, drain, and gate electrodes.^[39] To enable patterning at pitches below 10 nm, self-aligned double patterning (SADP) emerged as a key adaptation, leveraging spacer-defined lithography to double the resolution of 193 nm immersion tools without requiring multiple exposures. The process involves depositing a mandrel layer to define coarse patterns, followed by conformal deposition of a sidewall spacer film (typically silicon nitride or oxide), anisotropic etching to form spacers, and selective mandrel removal, resulting in self-aligned fine lines with enhanced overlay tolerance and reduced edge placement errors. This technique has been critical for gate and contact layers in nodes from 14 nm onward, facilitating denser interconnects while integrating seamlessly with self-aligned gate formation.^[40] Short-channel effects, including drain-induced barrier lowering (DIBL), necessitated refinements in doping strategies for nodes at 90 nm and below. Halo implants, or pocket doping, were introduced to create localized high-doping pockets adjacent to the source and drain regions under the gate edges, enhancing threshold voltage control and suppressing subthreshold leakage without significantly impacting long-channel performance. Performed at high tilt angles using the gate as a self-aligned mask, these angled boron (for nMOS) or phosphorus (for pMOS) implants form non-uniform doping profiles that counteract carrier injection from the drain, enabling reliable operation at gate lengths below 50 nm.^[41] The evolution of self-aligned gates extended beyond planar transistors to three-dimensional structures, such as FinFETs, which wrap the gate around multiple fins for superior electrostatic control and reduced short-channel effects. This architectural shift, integrated with self-aligned processes for fin and gate definition, has enabled transistor densities exceeding 100 million per mm² in 5 nm nodes, as demonstrated by high-mobility channel FinFETs with EUV lithography.

Applications in Current Devices

Self-aligned gate technology remains a cornerstone in the fabrication of FinFETs at nodes of 14 nm and beyond, where the gate electrode wraps around the three-dimensional fin structure to enhance channel control and reduce short-channel effects. In Intel's 22 nm tri-gate process, introduced for high-performance computing and mobile applications, the self-aligned gate enables precise alignment with the fin, allowing for improved drive current and lower leakage compared to planar transistors, as demonstrated in early SoC implementations. Similarly, TSMC's 7 nm process employs FinFETs with self-aligned gates for mobile system-on-chips (SoCs), achieving higher transistor density and energy efficiency in devices like smartphone processors, where the gate patterning via self-aligned quadruple patterning supports aggressive scaling while maintaining manufacturability.^[42]^[43]^[44] Transitioning to gate-all-around field-effect transistors (GAAFETs) at advanced nodes, self-aligned gates fully encase nanosheet or nanowire channels, providing superior electrostatic control and mitigating leakage in high-performance computing environments. Samsung has integrated this approach in its 3 nm process, while TSMC is introducing it in its 2 nm (N2) process entering high-volume production in late 2025; Intel is also implementing GAAFETs through its RibbonFET technology in the 18A process node, on track for production in 2025. The gate is self-aligned to the stacked nanosheets to enable tighter pitch and better subthreshold swing, supporting applications in data centers and AI hardware where performance per watt is critical. This wrapping configuration improves drive current by up to 20-30% over FinFETs while enabling further scaling beyond 5 nm.^[45]^[46]^[47]^[48]^[49] In memory technologies, self-aligned gates are embedded in DRAM sense amplifiers and NAND flash cells to ensure precise pitch control and reliable operation at scaled dimensions. For DRAM, the self-aligned gate in peripheral sense amplifier transistors facilitates fast read/write speeds by minimizing overlap capacitances, as seen in embedded DRAM designs integrated with logic processes. In NAND flash, self-aligned shallow trench isolation and gate structures allow for high-density 3D stacking, with charge-trap or floating-gate cells benefiting from reduced variability in multi-level cell programming, enabling terabit-scale storage in consumer devices.^[50]^[51]^[52] As of 2025, self-aligned gate technology is integral to AI accelerators such as NVIDIA's Blackwell GPUs, fabricated on TSMC's 4NP enhanced 5 nm process to integrate 208 billion transistors, delivering significant power efficiency gains for training and inference workloads. These implementations, including the Blackwell architecture, rely on self-aligned gates for enhanced thermal management and performance scaling.^[53]^[54]

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Jan 18, 2017 · TSMC announced the “world's first 7nm CMOS platform technology for mobile system-on-a-chip (SoC) applications, featuring FinFET transistors”.<|separator|>
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Gate-All-Around FET (GAA FET) - Semiconductor Engineering
In IBM's gate-all-around fabrication process, two landing pads are formed on a substrate. ... Conventional self-aligned, nickel-based silicide contacts and copper ...
[43]
Samsung Begins Chip Production Using 3nm Process Technology ...
Jun 30, 2022 · Optimized 3nm process achieves 45% reduced power usage, 23% improved performance and 16% smaller surface area compared to 5nm process.Missing: self- aligned
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A Review of the Gate-All-Around Nanosheet FET Process ... - MDPI
Nov 3, 2022 · In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET are reviewed.
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Disturbance Characteristics of 1T DRAM Arrays Consisting of ...
May 28, 2023 · ... sense amplifier is used typically in the 1T DRAM architecture [25]. ... The intermediate n-doped channel region can be self-aligned with the gate ...
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Principle of Nand Flash Memory - Wiley Online Library
Dec 21, 2015 · One NAND string consists of 32 series-connected stacked gate memory transistors and two select gate transistors. ... A self-aligned STI ...
[47]
Characteristics of Sub-50 nm NAND Flash Devices with Various Self ...
Aug 6, 2025 · The program efficiency and endurance characteristics of sub-50nm NAND flash devices with various self-aligned shallow trench isolation ...Missing: DRAM sense amps
[48]
Nvidia's Jensen Huang expects GAA-based technologies to bring a ...
N2 — to increase performance by 10% to 15% compared to N3E, the company's second ...
[49]
TSMC N3, And Challenges Ahead - WikiChip Fuse
May 27, 2023 · One of the things TSMC introduced with their N3B node is a new self-aligned contact (SAC) scheme. ... Samsung 3nm GAAFET Enters Risk Production; ...<|separator|>