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130 nm process

The 130 nm process, also denoted as the 0.13 μm process, is a semiconductor manufacturing technology node in integrated circuit fabrication, defined by a typical metal half-pitch and transistor gate length scaling to approximately 130 nanometers, which enabled substantial improvements in transistor density, speed, and power efficiency compared to prior nodes like 180 nm.^[1] This node was first introduced in 2001 by leading foundries and integrated device manufacturers including Intel, IBM, Texas Instruments, and TSMC, with Samsung initiating mass production in 2002.^[2]^[3] Key characteristics of the 130 nm process include physical gate lengths ranging from 45 nm for high-performance microprocessors (MPUs) to 65-90 nm for application-specific integrated circuits (ASICs) and low-power variants, alongside printed gate lengths of 65-90 nm.^[1] It commonly incorporated advanced features such as 70 nm transistors with 1.5 nm gate oxide thickness, dual threshold voltage (Vt) options for balancing speed and leakage (high Vt NMOS drive current of 1.03 mA/μm and low Vt of 1.17 mA/μm at 1.3 V), and up to six layers of dual damascene copper interconnects using low-k fluorinated SiO₂ dielectrics (k=3.6) to reduce capacitance and signal delay.^[4] Supply voltages were standardized at 1.2 V for high-performance applications and 1.0 V for low operating power scenarios, supporting ring oscillator delays as low as 7 ps/stage and SRAM densities up to 2.09 μm² per 6-T cell.^[1]^[4] The process facilitated the production of system-on-chip (SoC) designs integrating ultra-small SRAM, embedded flash (eFlash), bipolar-CMOS-DMOS (BCD) for power management, and display driver interfaces (DDI), making it particularly suitable for microcontrollers (MCUs), wearable devices, Internet of Things (IoT) applications, early mobile processors, and modern automotive semiconductors, as evidenced by Siemens' 2025 collaboration with SK Keyfoundry on a Calibre PERC PDK for 130 nm automotive power devices.^[5]^[3]^[6] According to the 2003 International Technology Roadmap for Semiconductors (ITRS), the 130 nm node adhered to a two-year cycle from the 180 nm generation, accelerating Moore's Law trends and paving the way for subsequent shrinks to 90 nm by 2004.^[1] Despite its maturity, variants of the 130 nm process remain highly relevant in 2025, exemplified by Texas Instruments' announcement of a $60 billion investment in new U.S. fabs dedicated to 130 nm production for automotive, industrial, and other applications beyond GPUs, as well as ongoing use in cost-effective, analog-optimized, and low-power embedded systems where extreme scaling is unnecessary.^[7]^[3]

Overview

Introduction

The 130 nm process represents a key generation in semiconductor manufacturing technology, characterized by a minimum feature size of 130 nanometers, specifically referring to the half-pitch of metal lines in the first interconnect layer or the dimensions of contact holes. This node marked a significant advancement in integrated circuit fabrication, with initial development and prototyping occurring around 2000, leading to production readiness by 2001.^[1]^[8] Major semiconductor companies, including Intel, Texas Instruments, IBM, and TSMC, were instrumental in pioneering and commercializing the 130 nm process in 2001, transitioning from the preceding 180 nm node that had been established in the late 1990s. This introduction enabled the fabrication of more complex chips on 300 mm wafers for some implementations, building on earlier 200 mm wafer standards.^[2]^[8]^[9] The 130 nm node played a crucial role in sustaining Moore's Law by achieving a linear scaling factor of approximately 0.7x compared to the 180 nm generation, which translated to roughly double the transistor density, improved clock speeds, and reduced power consumption per device. This progression paved the way for the subsequent 90 nm node introduced in 2004, further advancing computational capabilities in microprocessors and other electronics.^[1]^[10]^[11]

Historical Development

Research on the 130 nm semiconductor process began in the late 1990s as part of the industry's push toward sub-150 nm nodes to sustain Moore's Law scaling.^[2] By November 7, 2000, Intel announced the completion of development for its 0.13 micron (130 nm) logic technology, known internally as the P860 process, which incorporated copper interconnects and low-k dielectrics to enable higher transistor densities and speeds.^[8] This marked one of the first major announcements from leading manufacturers, with Intel planning volume production on 200 mm wafers starting in 2001, followed by 300 mm wafers in 2002.^[8] TSMC similarly advanced its efforts, announcing in January 2001 its intention to integrate CVD-based low-k dielectrics into its 0.13-micron copper process, positioning it as a pioneer in foundry adoption.^[12] The International Technology Roadmap for Semiconductors (ITRS) played a pivotal role in accelerating the 130 nm node's timeline, pulling it forward from a projected 2002 introduction in the 1999 roadmap to 2001 in the 2000 and 2001 editions, driven by aggressive industry trends toward faster node cycles.^[1] This adjustment reflected a shift to two-year cycles for logic technologies, anticipating rapid advancements in lithography and materials to meet escalating performance demands.^[1] Commercial ramp-up followed swiftly, with Intel initiating production in 2001 and releasing its first 130 nm chips, such as the Pentium III Tualatin processors, by late that year to demonstrate the technology's viability.^[13] TSMC achieved volume production of its 0.13-micron copper process in 2001, with low-k dielectric integration entering production in 2002 ahead of many peers, while Samsung began mass production in 2002, focusing on logic applications.^[12]^[3] Key industry drivers for the 130 nm adoption included surging demand for higher-speed microprocessors in personal computers and emerging mobile devices, which outpaced the capabilities of the prior 180 nm node in terms of density and power efficiency.^[14] The rise of system-on-chip (SoC) designs for consumer electronics and communications further necessitated the transition, as multi-core architectures and integrated functionalities began emerging at this node to support broadband internet, portable computing, and early wireless applications.^[14] These pressures, combined with competitive scaling from DRAM and MPU sectors, compelled manufacturers to prioritize 130 nm for enabling gigahertz-era processors and cost-effective scaling beyond 180 nm limitations.^[15]

Technical Specifications

Lithography and Scaling

The 130 nm process node utilized 248 nm KrF (krypton fluoride) deep ultraviolet (DUV) lithography systems for critical layers such as poly gates and contacts, enabling resolutions approaching the sub-130 nm half-pitch required for dense patterning.^[16] This KrF implementation, with numerical apertures up to 0.80, leveraged optimized resists and illumination schemes to achieve the necessary depth of focus for feature printing. Although full immersion lithography emerged later for finer nodes, dry KrF at 130 nm provided sufficient margin for high-volume manufacturing when combined with resolution enhancement techniques (RETs).^[17] Scaling in the 130 nm node emphasized dimensional reductions beyond the nominal name, with metal line half-pitches of approximately 170 nm for Metal 1 in MPU/ASIC applications to support interconnect density while maintaining yield.^[1] Gate length scaling proved particularly aggressive, achieving effective lengths of around 70 nm in high-performance variants, with physical gate dimensions etched to 60-70 nm as demonstrated in Intel's implementation featuring 1.5 nm gate oxides.^[16] TSMC's parallel efforts similarly targeted 60-70 nm physical gates, enabling transistor densities of approximately 300,000 to 500,000 per square millimeter in logic applications.^[4] These metrics reflected a departure from strict linear scaling, prioritizing performance gains through effective channel length control over nominal node adherence.^[10] To resolve features at these scales using longer wavelengths, resolution enhancement techniques (RETs) became integral, including optical proximity correction (OPC) to mitigate diffraction-induced distortions in dense patterns. Attenuated phase-shift masks (attPSM) were widely applied for gate-level patterning, enhancing contrast by introducing 180-degree phase shifts in sub-resolution assist features to sharpen edges without multiple exposures.^[18] Early precursors to multiple patterning, such as scattering bars and off-axis annular illumination, further extended KrF capabilities, achieving process windows viable for 130 nm production while minimizing mask complexity.^[19] These RETs collectively reduced k1 factors below 0.5, ensuring manufacturability despite the optical challenges of sub-wavelength lithography.^[20] Wafer fabrication at the 130 nm node primarily utilized 200 mm (8-inch) substrates to leverage existing infrastructure and cost efficiencies, supporting the bulk of high-volume production across foundries like TSMC.^[21] Toward the latter part of the node's lifecycle around 2002-2003, initial pilots transitioned to 300 mm (12-inch) wafers, as pioneered by Intel to capture a projected 30% cost reduction through higher die yields per wafer.^[22] This shift laid groundwork for broader 300 mm adoption in subsequent nodes, though 200 mm remained dominant for 130 nm due to tool compatibility and lower upfront investment.^[23]

Transistor and Device Features

The 130 nm process predominantly employed complementary metal-oxide-semiconductor (CMOS) technology, with core transistors featuring gate lengths of 60–70 nm to achieve enhanced density and switching speeds. This gate length scaling, combined with optimized source/drain extensions, allowed for improved drive currents while controlling short-channel effects. A key innovation was the introduction of dual-threshold voltage (dual-Vt) transistors, which utilized low-Vt devices for high-speed logic paths and high-Vt devices for leakage-sensitive areas, enabling a 20–30% performance boost without excessive power dissipation, as implemented in Intel's 130 nm logic platform. The gate stack typically consisted of polysilicon gates over a thin silicon dioxide (SiO2) or nitrided oxide dielectric with equivalent oxide thickness (EOT) of approximately 1.5–2.5 nm, providing sufficient gate control for sub-100 nm dimensions while minimizing tunneling leakage. Channel engineering techniques, including angled halo (pocket) implants and lightly doped drains (LDD), were integral to this node, enhancing carrier mobility by up to 15–20% through reduced impurity scattering and better threshold voltage roll-off control. Although production devices stuck with SiO2-based stacks, research during the 130 nm era explored high-k precursors like hafnium-based oxides to address scaling limits, demonstrating potential EOT reductions below 1 nm in lab prototypes.^[16] Embedded static random-access memory (SRAM) cells benefited significantly, with 6-transistor (6T) designs achieving areas of 1.9–3 μm², supporting gate densities over 200 kcells/mm² and enabling larger on-chip caches in system-on-chip (SoC) applications without compromising stability. These compact cells relied on matched dual-Vt transistors to maintain static noise margins above 100 mV at nominal operation. The process operated at a nominal supply voltage of 1.3 V for core logic, facilitating ring oscillator frequencies exceeding 40 GHz and enabling microprocessor clock speeds over 3 GHz in high-performance configurations.

Interconnects and Materials

In the 130 nm process node, copper (Cu) became the standard interconnect metal, replacing aluminum due to its lower resistivity and improved scalability for high-speed applications.^[16] Typical implementations featured 6 to 8 metal layers to support complex routing in system-on-chip (SoC) designs. For instance, Intel's 130 nm process utilized six layers of Cu interconnects, enabling high-density integration for microprocessors.^[24] Similarly, TSMC's 0.13 μm technology incorporated eight layers of low-k Cu interconnects, optimizing signal integrity and power delivery in high-performance logic.^[25] Dielectrics in 130 nm interconnects introduced low-k materials such as fluorinated silicate glass (FSG) with k ≈ 3.7 to mitigate RC delay as feature sizes shrank, with some processes adopting carbon-doped oxides (such as SiOCH or CDO, k ≈ 2.8) for further capacitance reduction in performance-critical paths.^[26]^[27]^[28] These materials were integrated via chemical vapor deposition (CVD) to form inter-level dielectrics (ILD), balancing electrical performance with mechanical stability during multi-layer stacking. Contacts to active devices and vias between metal layers employed tungsten (W) plugs, providing reliable low-resistance connections while preventing Cu diffusion into silicon.^[16] The damascene process was standard for patterning Cu lines and vias, where trenches and holes are etched into the dielectric, filled with electroplated Cu, and planarized via chemical mechanical polishing (CMP) to enhance electromigration resistance compared to earlier subtractive etching methods.^[24] A key innovation was the dual damascene integration scheme for Cu interconnects, which simultaneously patterns lines and vias in a single lithography and etch sequence, reducing process steps and enabling tighter pitches.^[24] This approach yielded lower sheet resistance (ρ ≈ 2.0 μΩ·cm for Cu lines) than aluminum interconnects in prior nodes (ρ ≈ 3.0 μΩ·cm), supporting faster signal propagation and higher current densities in 130 nm devices.^[16]

Manufacturing Process

Key Steps and Integration

The fabrication process for 130 nm CMOS integrated circuits commences with substrate preparation, utilizing a highly doped p-type silicon wafer to minimize latch-up risks, often followed by epitaxial growth of a lightly doped layer for optimized device performance. Shallow trench isolation (STI) is then implemented to electrically separate transistors, involving the etching of trenches approximately 300-450 nm deep, deposition of silicon dioxide via chemical vapor deposition (CVD), and subsequent planarization using chemical mechanical polishing (CMP) to achieve a flat surface for overlying layers.^[29]^[16] Following isolation, dual well implantation establishes n-wells and p-wells through phosphorus or boron doping, respectively, with annealing to activate and diffuse the implants. Gate formation proceeds with thermal oxidation to grow a thin silicon dioxide layer (typically 1.5-2.2 nm thick), followed by low-pressure CVD deposition of polycrystalline silicon (poly-Si) for the gate electrode, which is patterned using lithography and plasma etching to define 60-90 nm gate lengths. Source and drain regions are created via self-aligned low-dose drain (LDD) implants using arsenic for nMOS or boron for pMOS, sidewall spacer formation from oxide or nitride, high-dose source/drain implants, and halo implants to control short-channel effects, culminating in cobalt or nickel silicide contacts for reduced resistance.^[29]^[16]^[4] The back-end-of-line (BEOL) processing integrates copper damascene metallization for interconnects, typically comprising 5-6 layers with a tungsten or tantalum nitride barrier to prevent diffusion, electrochemical copper deposition, and CMP for each level to ensure planarity and minimize defects. Low-k dielectrics, such as fluorinated silicon dioxide (k ≈ 3.0-3.6), replace traditional SiO₂ to reduce capacitance, followed by final passivation with plasma-enhanced CVD silicon nitride to protect against moisture and contaminants.^[16]^[30] Key integration innovations at the 130 nm node enabled system-on-chip (SoC) platforms by combining logic, embedded SRAM, and analog components through multiple CMOS transistor variants on a single die, as exemplified by TSMC's low-k copper process supporting ultra-small SRAM cells and mixed-signal functionality. CMP played a pivotal role in planarizing both STI and damascene structures, mitigating topography-induced defects and enabling denser layouts.^[25]^[31] Yield optimization faced significant challenges from 193 nm lithography alignment precision, which was newly adopted for critical layers to achieve sub-130 nm features, and low-k dielectric integration issues including copper diffusion through porous materials, poor adhesion to barriers, and mechanical fragility during CMP. These hurdles were addressed through refined barrier layers and process controls, leading to yields exceeding 80% in mature production by 2002 and enabling high-volume manufacturing.^[32]^[33]^[34] Process variants tailored the technology for diverse applications, with high-performance (HP) configurations optimized for microprocessors featuring low threshold voltage (Vt ≈ 0.3-0.4 V) and thin gate oxide (≈1.5-1.6 nm) to maximize drive current, contrasted by low-power (LP) variants for mobile devices employing higher Vt (≈0.5 V) and thicker oxide (≈2.0 nm) to suppress leakage while maintaining compatibility with the core flow. Dual-Vt transistor options further enhanced flexibility by integrating both types on-chip for critical path speed and standby power savings.^[35]^[4]

Performance Metrics and Variations

The 130 nm process node delivered notable advancements in transistor performance, with drive currents typically ranging from 1.0 to 1.2 mA/μm for NMOS devices at a 1.3 V supply voltage, enabling high-speed logic operation while balancing power efficiency.^[4] Leakage control was achieved through dual-threshold voltage (dual-Vt) transistor designs, where high-Vt devices limited off-state leakage to below 10 nA/μm, reducing static power dissipation in standby modes without severely impacting dynamic performance.^[16] Power density for logic circuits hovered around 1 W/mm² under nominal operating conditions, reflecting the challenges of scaling while maintaining thermal manageability in dense integrations.^[1] Transistor density in 130 nm logic reached approximately 4-6 million transistors per mm², supporting complex system-on-chip designs with improved integration over prior nodes.^[1] For embedded memory, SRAM cell densities achieved 0.3-0.4 Mb/mm², facilitated by compact 6T cell layouts around 2.45 μm², which enhanced yield and area efficiency in high-volume production.^[8] Manufacturer-specific variations optimized the 130 nm process for diverse applications. Intel's P860 process operated at 1.3 V and supported clock speeds exceeding 1.5 GHz in logic circuits, leveraging dual-Vt and copper interconnects for robust high-performance computing.^[8] TSMC's implementation incorporated low-k dielectrics with copper metallization, providing speed improvements through reduced interconnect capacitance and resistance, ideal for mixed-signal SoCs.^[36] Samsung emphasized low-power variants of the 130 nm node, tailored for wearable and IoT devices with enhanced power management to minimize consumption in battery-constrained environments.^[3] Reliability metrics underscored the node's maturity, with electromigration lifetimes exceeding 10 years under typical operating currents and temperatures, ensured by optimized Cu damascene structures and barrier layers.^[37] Thermal stability extended to 125°C for extended operation, qualifying the process for automotive and industrial uses where junction temperatures could rise significantly during stress.^[38]

Applications and Products

Microprocessors and CPUs

The 130 nm process enabled significant advancements in microprocessor design, particularly for desktop and mobile CPUs, by allowing higher transistor densities and improved power efficiency compared to prior nodes. Intel's Pentium III Tualatin core, released in 2001, represented one of the earliest implementations, operating at clock speeds up to 1.4 GHz with a 256 KB L2 cache. This transition to 130 nm from the previous 180 nm Coppermine core facilitated better performance in compact form factors. Similarly, the Pentium 4 Northwood core, introduced in January 2002, scaled to speeds between 1.8 GHz and 3.4 GHz while doubling the L2 cache to 512 KB, enhancing overall system responsiveness and enabling larger on-die memory for improved branch prediction and data access. The first Xeon processors on 130 nm, codenamed Prestonia and launched in February 2002, supported up to 3.06 GHz with Hyper-Threading technology, targeting server and workstation applications with enhanced multi-tasking capabilities. AMD leveraged the 130 nm node for its Athlon XP Thoroughbred core, debuting in 2002 at speeds up to 2.25 GHz (as in the 2800+ model) with a 256 KB L2 cache, which provided a competitive edge in consumer desktops through higher clock rates and reduced power draw relative to 180 nm predecessors. The budget-oriented Duron line followed with the Applebred core, also on 130 nm, reaching up to 1.8 GHz and maintaining compatibility with Socket A platforms for cost-effective computing. These AMD designs contributed to the era's push toward gigahertz-class performance in mainstream PCs. IBM and Motorola's collaboration produced notable PowerPC G4 variants on 130 nm, including the MPC7447 and MPC7457 cores introduced in 2002, which operated up to around 1 GHz with a 512 KB L2 cache using silicon-on-insulator (SOI) technology for lower power consumption. These processors powered embedded and Apple systems, emphasizing vector processing for multimedia tasks. Overall, the 130 nm process facilitated the first widespread GHz+ mobile CPUs, such as AMD's Mobile Athlon XP at up to 1.5 GHz, marking a key step in portable computing efficiency.

Other ICs and Devices

The 130 nm process found extensive application in system-on-chip (SoC) and application-specific integrated circuit (ASIC) designs, particularly for wireless baseband processors and multimedia processing units in early mobile devices. TSMC's 0.13 μm SoC low-k copper technology supported the integration of high-performance logic with embedded memory, enabling compact designs for wireless communication chips that handled baseband signal processing in GSM-compliant systems.^[25]^[39] For instance, early smartphone SoCs leveraged this node to combine baseband functionality with multimedia acceleration, facilitating the transition from feature phones to more capable handheld devices. Low-power variants of the 130 nm process were optimized for personal digital assistants (PDAs), incorporating power management IP to support battery-constrained applications like Bluetooth connectivity in single-chip solutions.^[40]^[41] In memory applications, the 130 nm process enabled the development of DDR SDRAM controllers and embedded non-volatile storage, providing efficient interfaces for data-intensive ICs. Renesas' CB-130 platform integrated DDR-SDRAM controllers alongside SRAM, ROM, and flash memory options, allowing for versatile memory hierarchies in ASICs used in consumer electronics.^[42] Embedded flash solutions, such as Infineon's SONOS-based eFlash, were produced at this node starting from 2001, offering reliable non-volatile storage for automotive and industrial controllers with densities suitable for code storage and data retention.^[43] Additionally, SRAM blocks were a core feature in field-programmable gate arrays (FPGAs) like Xilinx's Virtex-II Pro family, which utilized 130 nm CMOS to deliver configurable logic with up to several megabits of on-chip SRAM for high-speed buffering and lookup tables in networking and signal processing applications.^[44] The 130 nm node proved particularly advantageous for analog and power management ICs, where high-voltage devices supported demanding environments like automotive and Internet of Things (IoT) systems. A 130 nm BCD (Bipolar-CMOS-DMOS) smart-power technology incorporated high-voltage transistors rated up to 60 V, alongside embedded flash and logic, enabling integrated solutions for motor drivers and power conversion in vehicles.^[45]^[46] GlobalFoundries' 130 nm BCDLite process facilitated power management ICs for sensors and actuators, balancing performance with cost for IoT edge devices.^[47] These capabilities extended to sensors and power ICs, where the mature node's cost-effectiveness—stemming from established yields and minimal redesign needs—continued to support production for low-volume, high-reliability applications in IoT, including embedded non-volatile memory solutions like Weebit ReRAM integrated in SkyWater's 130 nm process as of 2025.^[48] Notable implementations included programmable logic devices from Altera (now Intel), such as the Cyclone family FPGAs fabricated in 130 nm CMOS, which provided flexible reconfigurable computing for embedded systems with integrated I/O and low static power. RF transceivers also benefited from the process, with designs like ultra-low-power 2.4 GHz receivers for wireless sensor networks achieving operation down to 400 mV supply voltage in 130 nm CMOS, supporting short-range connectivity in IoT nodes. X-FAB's 130 nm RF-SOI platform delivered low-noise, high-isolation performance for multi-band transceivers in mobile and automotive radios. Legacy 130 nm support has persisted in various applications, including GlobalFoundries' 130 nm CBIC platform for high-performance RF and industrial uses, with multi-project wafer shuttles available through 2025. In August 2025, GlobalFoundries announced the production release of its advanced 130 nm complementary Bi-CMOS (CBIC) SiGe platform, featuring NPN transistors exceeding 400 GHz ft/fmax to push RF performance limits for specialized applications in smart mobile communications, wireless infrastructure, and industrial IoT.^[49] Microchip's IGLOO Nano FPGAs in 130 nm further enabled energy-efficient logic in wearable prototypes with flash-based configuration for reduced power draw.^[50]^[51]^[52]^[53]

Legacy and Comparisons

Evolution from Prior Nodes

The 130 nm process node marked a significant advancement in semiconductor scaling, primarily over the preceding 180 nm node, with the 150 nm serving as an intermediate "half-node" that offered modest refinements but did not fully realize the density and performance leaps of the 130 nm generation.^[54] Transistor density for high-performance logic roughly doubled from approximately 0.61 million transistors per mm² at the 180 nm node to around 1.22 million transistors per mm² at 130 nm, enabling integration of about twice as many transistors in the same die area compared to 180 nm designs.^[1] This ~2× density increase was driven by linear dimension scaling of approximately 0.7× (from 180 nm to 130 nm), which reduced feature sizes for gates, contacts, and interconnects while maintaining compatibility with existing design rules. The 150 nm node, by contrast, achieved only an intermediate density uplift of about 20-30% over 180 nm, as it primarily optimized existing 180 nm flows without introducing major architectural changes.^[1] Performance enhancements in the 130 nm node included speed gains of 20-30% in clock frequency over 180 nm equivalents, allowing typical microprocessor clocks to rise from around 1 GHz to 1.5 GHz or higher at similar voltages.^[16] These uplifts stemmed from shorter gate lengths (e.g., 60 nm vs. 70 nm at 180 nm) and the integration of low-k dielectrics, which minimized parasitic capacitance and improved signal propagation.^[16] The 150 nm node provided smaller gains, typically 10-15% in frequency, as it retained much of the 180 nm transistor architecture without aggressive scaling.^[54] Power efficiency improved notably in the 130 nm process through the widespread adoption of copper interconnects and low-k materials, which reduced dynamic power consumption by lowering RC delays by over 30% compared to the aluminum and silicon dioxide (SiO₂) stacks dominant in 180 nm technologies. Copper's lower resistivity (about 40% less than aluminum) combined with low-k inter-layer dielectrics (k ≈ 3.0-3.6 vs. 4.0 for SiO₂) decreased interconnect resistance and capacitance, enabling 50% overall RC reduction in some implementations relative to 180 nm aluminum-based wiring.^[16] This shift also marked the definitive end of aluminum interconnect dominance, as copper became the standard for multi-layer (e.g., six-layer) routing in 130 nm, a transition that the 150 nm node only partially initiated in select high-volume processes.^[16] These technical evolutions facilitated architectural shifts, making larger on-die caches (e.g., multi-megabit SRAM arrays) and deeper pipelines more feasible due to the enhanced density and reduced interconnect delays.^[16] Prior to 130 nm, 180 nm limitations on area and power often constrained such features to off-chip solutions, but the node's improvements supported integrated system-on-chip (SoC) designs with substantially larger on-chip memory, aligning with scaling roadmaps that emphasized integration over isolated component optimization.^[1]

Transition to Successor Nodes and Ongoing Use

The transition to the 90 nm process node marked a significant advancement in semiconductor manufacturing, beginning with Intel's introduction of the Prescott-core Pentium 4 processors in February 2004.^[55] This shift phased out the 130 nm node for leading-edge applications by around 2005, as major foundries and integrated device manufacturers prioritized the smaller geometry for higher density and performance in digital logic.^[2] Intermediate variants, such as the 110 nm process introduced as a half-node bridge by some manufacturers in 2003, helped smooth the migration by offering incremental improvements in yield and cost before full adoption of 90 nm.^[56] Key differences between the 130 nm and 90 nm nodes included innovations in transistor performance and fabrication scale. The 90 nm process incorporated strained silicon channels, which enhanced carrier mobility and boosted NMOS and PMOS drive currents by 10-20%, enabling faster operation without proportional increases in power consumption.^[57] Additionally, production shifted from predominantly 200 mm wafers at 130 nm to 300 mm wafers at 90 nm, allowing for greater throughput and cost efficiencies in high-volume manufacturing.^[23] Despite the move to advanced nodes, the 130 nm process retains ongoing relevance in 2025, particularly for legacy analog, mixed-signal, and cost-sensitive applications such as IoT devices and automotive sensors, where high reliability and lower development costs outweigh the need for cutting-edge density.^[23] Foundries like TSMC continue production on dedicated facilities, such as Fab 10, supporting 130 nm alongside other mature nodes for low-volume, high-reliability needs.^[58] Similarly, UMC maintains 130 nm capacity through joint ventures like SSMC, catering to mixed-signal and power management ICs.^[59] The 130 nm node played a pivotal role in enabling the early 2000s mobile revolution by powering baseband processors and RF components in 3G handsets, and today it constitutes a portion of the mature node market, which is projected to see 6% capacity growth in 2025 driven by demand in automotive and industrial sectors.^[60]

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In this work, we investigated the causes of electrical yield loss of wafers fabricated from Cu/CVD low k SiOCH interconnect. Yield improvement from the study of ...
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Integration Challenges for CMP of Copper - SpringerLink
Jan 31, 2011 · As the minimum feature size of microelectronic devices shrinks down to 130 nm, copper has been successfully adopted into logic applications.
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Low-k issues plague transition to 130 nm - EDN
Major silicon vendors are still struggling to forge a viable interconnect strategy at this late stage in the 130-nanometer (0.13-micron) technology development ...
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Low-k issues plague transition to 0.13-micron processes - EE Times
Moving past silicon dioxide to low-k dielectrics to insulate copper interconnects is proving far more difficult than many had envisioned. Major ...
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A Trip Down TSMC Memory Lane – Part 2 | TechInsights
Having slowed down a bit at 130 nm, not using low-k , and belatedly moving to copper metal, Intel arguably took the technology lead with the introduction of ...
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[PDF] Low-noise Design Issues for Analog Front-end Electronics in 130 ...
In the 130 nm process PMOS and NMOS devices with gate length L of 0.13, 0.2, 0.35, 0.5, 0.7 and 1 μm, and gate width W of 200, 600 and 1000 μm were investigated ...
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TSMC reworks low-k process - EE Times
Apr 26, 2004 · Low-k dielectrics deliver about a 10 percent performance improvement over fluorinated silicate glass, the more prevalent insulator, company ...
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Investigating the electromigration limits of Cu nano-interconnects ...
Aug 1, 2019 · ... lifetime of 10 years), which is 2.7 MA/cm2 and 0.3 MA/cm2 for the 130 nm wide and 10 nm wide interconnects, respectively.23 The simulations ...
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[PDF] Cryogenic Lifetime Studies of 130 nm and 65 nm CMOS ...
For reasons of efficiency and economics, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of ...
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A GSM Baseband Radio in 0.13μm CMOS with Fully Integrated ...
Aug 5, 2025 · A GSM-compliant baseband radio with integrated power-management unit (PMU) is fabricated in a 0.13μm CMOS process.
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Power management IP: Coming to the rescue for nanometer design
Aug 1, 2004 · The faster speed of the 130-nm process will offset the loss of performance of the low-power IP. For current-generation wireless baseband ...
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[PDF] Bluetooth® Solutions from Texas Instruments
Based on TI's 130-nm CMOS process, the BRF6100 is TI's Bluetooth specification v1.1 certified (over -40 to +85 degrees) single-chip solution. The device ...Missing: variants | Show results with:variants<|separator|>
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https://www.ti.com/pdfs/wtbu/TI_brf6100_6150.pdf
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Embedded flash IP solutions | Infineon Technologies
Since its launch in 2001 on 350 nm, SONOS embedded flash has progressed and is now available in volume production on various advanced nodes, including 130 nm, ...
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[PDF] DS031 - Virtex-II Platform FPGAs: Complete Data Sheet - MIT
Mar 1, 2005 · The Virtex-II family is a platform FPGA developed for high performance from low-density to high-density designs that are based on IP cores and ...<|separator|>
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Xilinx Virtex-II Pro World's Most Popular 130nm FPGA
The Xilinx Virtex-II Pro family is the world's first FPGA to offer integrated PowerPC embedded technology and 3.125 Gbps serial transceivers. Virtex-II Pro ...Missing: SRAM | Show results with:SRAM
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[PDF] Automotive 130 nm Smart-Power-Technology including embedded ...
The BCD process presented also offers a three layer dual- damascene copper metallization and a single-damascene copper layer with tungsten plugs. This metal ...
[46]
Automotive 130 nm smart-power-technology including embedded ...
This paper highlights the general trend towards further monolithic integration in power applications by enabling power management and interfacing solutions ...Missing: IoT sensors
[47]
Audio & Power Management | GlobalFoundries
Power management ICs using 55, 130 and 180 nm BCDLite solutions. The GF portfolio of BCDLite power management solutions spans nodes ranging from 55 nm to 180 nm ...
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https://www.weebit-nano.com/wp-content/uploads/2025/10/Weebit-embedded-RRAM-ReRAM-IP-NVM-semiconductors-SkyWater-130nm-CMOS-technology-production_PB_Rev.-OCT25P.pdf
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EP1C12F256C8 Altera Cyclone FPGA 12060 185 I/O 8 ... - eBay
In stock Free deliveryHere are some specs: Filed Programmable Gate Array; Cyclone Family; 12060 Cells; 185 I/O; 130nm; 1.5V to 3.3V Supply; 8 Speed ...
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https://ieeexplore.ieee.org/document/1696196/
[51]
RF and wireless solutions from a foundry: X-FAB
Our RF SOI technology is made available through a 130 nm feature-rich, modular RF platform that allows you to achieve low-loss, high-isolation and low-noise RF ...
[52]
SkyWater Chosen for Volume U.S. Manufacturing of Temperature ...
May 26, 2020 · A microchip with temperature sensing capabilities used in a low-cost, smartphone-enabled wireless patch that assists in the remote detection of COVID-19.Missing: legacy | Show results with:legacy<|control11|><|separator|>
[53]
IGLOO® FPGAs - Microchip Technology
The IGLOO /e family of low-power Flash FPGAs, which is based on a 130 nm Flash process, is a single-chip reprogrammable solution that offers an abundance of ...
[54]
[PDF] 2001 Format for ITRS - Semiconductor Industry Association
In addition, some companies may choose to introduce a “half node” (for example 150 nm may be considered a half node between the 180 nm node and the 130 nm node) ...
[55]
Intel Introduces Intel® Pentium® 4 Processors On High-Volume 90 ...
SANTA CLARA, Calif., Feb. 2, 2004 - Intel Corporation is delivering four new processors (formerly codenamed Prescott) that are built on the company's industry- ...
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110 nm lithography process - WikiChip
Jul 20, 2018 · The 110 nanometer (110 nm) lithography process is a half-node semiconductor manufacturing process used as a stopgap between the 130 nm and 90 nm processes.Missing: bridge | Show results with:bridge
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Strained Transistors - REFERENCE PMOS-strained - Intel
Intel made a significant breakthrough in the 90nm process generation by introducing strained silicon on both the N and PMOS transistors.
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https://www.blackridgeresearch.com/blog/list-of-tsmc-fabs-in-taiwan-arizona-kumamoto
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UMC Reports Sales for August 2025 | SemiWiki
Sep 4, 2025 · Based on available information, SSMC produces chips using process geometries ranging from 0.35μm (350nm) to 0.13μm (130nm). These nodes are ...
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Mature Process Capacity to Grow 6% in 2025 - TrendForce
Oct 24, 2024 · It is estimated that the capacity of the world's top 10 mature process foundries will increase by 6% in 2025, though pricing pressures will persist.
[61]
Texas Instruments plans to invest more than $60 billion to manufacture billions of foundational semiconductors in the US
Official press release from Texas Instruments announcing plans to invest over $60 billion in U.S. semiconductor manufacturing facilities, including production for 130 nm process nodes targeted at automotive, industrial, and other applications.
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SK keyfoundry to launch 130nm Calibre PERC PDK | Siemens
Siemens official press release announcing collaboration with SK keyfoundry to launch 130nm automotive power semiconductor Calibre PERC PDK on July 15, 2025.
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GlobalFoundries Announces Production Release of 130CBIC SiGe Platform
Official press release from GlobalFoundries announcing the production release of the 130 nm CBIC SiGe platform on August 28, 2025, detailing technical specifications and target applications.